AMD's Hammer's two extra Pipeline Stages
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Einen tieferen Einblick in die Architektur des K8 bietet Chip Architect
<ul><i>Raising the IPC of the Athlon core
The upcoming AMD Hammer family promises a significant increase in performance compared with the current generation of Athlon processors. Some of the increase comes from the low latency on chip memory controller, some of it comes from the extra architectural registers of the x86-64 instruction set and some comes from a number of new features that improve the ability of the Hammer micro-architecture to recognize a higher IPC ( Instructions executed Per Clock) than previous generation micro-architectures. Here we look into some depth into the latter.
Stretching the (Integer) pipeline from 10 to 12 stages
Two new pipeline stages are added to the pipeline. They are inserted directly after the stage where the x86 instructions have been either decoded, ( In case of the simpler 'RISC' like x86 instructions), or have started the micro code program from the micro code ROM. ( In the case of the more complex 'CISC' like x86 instructions) The new pipeline stages thus receive a stream of decoded instructions, either from the decoders or from the micro code ROM. </i></ul> Weitere Details könnt ihr direkt bei <a href="http://www.chip-architect.com/news/2002_06_24_Hammers_Two_Extra_PipelineStages.html" TARGET="b">Chip Architect</a> nachlesen.
<ul><i>Raising the IPC of the Athlon core
The upcoming AMD Hammer family promises a significant increase in performance compared with the current generation of Athlon processors. Some of the increase comes from the low latency on chip memory controller, some of it comes from the extra architectural registers of the x86-64 instruction set and some comes from a number of new features that improve the ability of the Hammer micro-architecture to recognize a higher IPC ( Instructions executed Per Clock) than previous generation micro-architectures. Here we look into some depth into the latter.
Stretching the (Integer) pipeline from 10 to 12 stages
Two new pipeline stages are added to the pipeline. They are inserted directly after the stage where the x86 instructions have been either decoded, ( In case of the simpler 'RISC' like x86 instructions), or have started the micro code program from the micro code ROM. ( In the case of the more complex 'CISC' like x86 instructions) The new pipeline stages thus receive a stream of decoded instructions, either from the decoders or from the micro code ROM. </i></ul> Weitere Details könnt ihr direkt bei <a href="http://www.chip-architect.com/news/2002_06_24_Hammers_Two_Extra_PipelineStages.html" TARGET="b">Chip Architect</a> nachlesen.
tHe_dAvEr
Fleet Captain Special
booooah krass
den will ich
den will ich
Original geschrieben von tHe_dAvEr
booooah krass
den will ich
ich glaube, du hast übersehen, daß dort von möglichen verbesserungen des IPC die rede ist. ausdrücklich wird gesagt, daß man nicht wisse ob und vor allem welche verbesserungen im k8 gegenüber dem k7 sind. also: am ende ist nur interessant, was hinten rauskommt. und 25% höherer ipc - warum auch immer - sind doch super...8)
p.s.: *angeb:* habe gerade meine IT-prüfung bestanden
AMD_Feuerspucker
Grand Admiral Special
Gratuliere!8) 8)
![mtb][sledgehammer](/data/avatars/m/1/1883.jpg?1596828194){kind=avatar}
mtb][sledgehammer
Grand Admiral Special
Ich hoffe doch, dass die 25% den "at worst case" beschreiben, dann sind in anderen Anwendungen auch 59% drin, bei SSE2 optimierter Software vielleicht auch 100%.
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