{"id":26005,"date":"2016-08-08T12:25:20","date_gmt":"2016-08-08T10:25:20","guid":{"rendered":"http:\/\/www.planet3dnow.de\/cms\/?p=26005"},"modified":"2016-08-08T12:25:20","modified_gmt":"2016-08-08T10:25:20","slug":"rambus-announces-silicon-proven-r-ddr4-phy-on-globalfoundries-14nm-lpp-process-for-networking-and-data-center-applications","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/26005-rambus-announces-silicon-proven-r-ddr4-phy-on-globalfoundries-14nm-lpp-process-for-networking-and-data-center-applications\/","title":{"rendered":"Rambus Announces Silicon-proven R+ <span class=\"caps\">DDR4<\/span> <span class=\"caps\">PHY<\/span> on <span class=\"caps\">GLOBALFOUNDRIES<\/span> 14nm <span class=\"caps\">LPP<\/span> Process for Networking and Data Center Applications"},"content":{"rendered":"<p><em>Pro\u00adduc\u00adtion-rea\u00addy <span class=\"caps\">PHY<\/span> <span class=\"caps\">IP<\/span> will address the high-per\u00adfor\u00admance needs of enter\u00adpri\u00adse systems<\/em><\/p>\n<p><strong><span class=\"caps\">SUNNYVALE<\/span>, Calif. \u2013 July 26, 2016 \u2013<\/strong> <a href=\"http:\/\/www.rambus.com\/\"><strong>Ram\u00adbus Inc.<\/strong><\/a> (<span class=\"caps\">NASDAQ<\/span>:<span class=\"caps\">RMBS<\/span>) today announ\u00adced that it has deve\u00adlo\u00adped an R+ <span class=\"caps\">DDR4<\/span> <span class=\"caps\">PHY<\/span> on the <span class=\"caps\">GLOBALFOUNDRIES<\/span> <span class=\"caps\">FX-14<\/span>\u2122 <span class=\"caps\">ASIC<\/span> plat\u00adform using the company\u2019s most advan\u00adced 14nm Power Plus (<span class=\"caps\">LPP<\/span>) pro\u00adcess. As part of a com\u00adpre\u00adhen\u00adsi\u00adve suite of memo\u00adry and Ser\u00adDes inter\u00adface offe\u00adrings for net\u00adwor\u00adking and data cen\u00adter appli\u00adca\u00adti\u00adons, Ram\u00adbus has achie\u00adved the first pro\u00adduc\u00adtion-rea\u00addy 3200 Mbps <span class=\"caps\">DDR4<\/span> <span class=\"caps\">PHY<\/span> available on <span class=\"caps\">GLOBALFOUNDRIES<\/span> power-per\u00adfor\u00admance opti\u00admi\u00adzed 14nm <span class=\"caps\">LPP<\/span> pro\u00adcess. The R+ <span class=\"caps\">DDR4<\/span> <span class=\"caps\">PHY<\/span> is desi\u00adgned to meet the per\u00adfor\u00admance and capa\u00adci\u00adty demands of the next wave of data cen\u00adter and net\u00adwor\u00adking markets.<\/p>\n<p><span class=\"dquo\">\u201c<\/span>As we beco\u00adme more reli\u00adant on the cloud and the stres\u00adses pla\u00adced on data cen\u00adters con\u00adti\u00adnues to grow, the need for memo\u00adry offe\u00adrings that pro\u00admi\u00adse fas\u00adter speeds and hig\u00adher band\u00adwidth has never been more important,\u201d said Luc Sera\u00adphin, seni\u00ador vice pre\u00adsi\u00addent and gene\u00adral mana\u00adger of the Ram\u00adbus Memo\u00adry and Inter\u00adfaces divi\u00adsi\u00adon. \u201cTog\u00ade\u00adther with <span class=\"caps\">GLOBALFOUNDRIES<\/span>, we have been able to deve\u00adlop the industry\u2019s first <span class=\"caps\">DDR4<\/span> <span class=\"caps\">PHY<\/span> on a 14nm <span class=\"caps\">LPP<\/span> pro\u00adcess run\u00adning at 3200 Mbps and capa\u00adble of achie\u00adving the per\u00adfor\u00admance requi\u00adre\u00adments of next-gene\u00adra\u00adti\u00adon systems.\u201d<\/p>\n<p><span class=\"dquo\">\u201c<\/span><span class=\"caps\">GLOBALFOUNDRIES<\/span>\u2019 <span class=\"caps\">FX-14<\/span>\u2122 plat\u00adform, based on our advan\u00adced 14nm <span class=\"caps\">LPP<\/span> tech\u00adno\u00adlo\u00adgy, is desi\u00adgned to sup\u00adport the memo\u00adry inten\u00adsi\u00adve com\u00adpu\u00adting tasks in today\u2019s most deman\u00adding enter\u00adpri\u00adse appli\u00adca\u00adti\u00adons,\u201d said Kevin O\u2019Buckley, vice pre\u00adsi\u00addent pro\u00adduct deve\u00adlo\u00adp\u00adment <span class=\"caps\">GLOBALFOUNDRIES<\/span>. \u201cAt 3200 Mbps, the R+ <span class=\"caps\">DDR4<\/span>\/3 <span class=\"caps\">PHY<\/span> deli\u00advers the maxi\u00admum data rate sup\u00adport\u00aded by the stan\u00addard enab\u00adling advan\u00adced func\u00adtion\u00ada\u00adli\u00adty like simul\u00adta\u00adneous strea\u00adming of Ultra <span class=\"caps\">HD<\/span> con\u00adtent. We look for\u00adward to con\u00adti\u00adnue col\u00adla\u00adbo\u00adra\u00adting with Ram\u00adbus as we deve\u00adlop a ful\u00adly-fea\u00adtured suite of memo\u00adry pro\u00adducts desi\u00adgned to ensu\u00adre the best per\u00adfor\u00admance for today\u2019s data centers.\u201d<\/p>\n<p>The Ram\u00adbus R+ <span class=\"caps\">DDR4<\/span> <span class=\"caps\">PHY<\/span> is <span class=\"caps\">DFI<\/span> 4.0 com\u00adpa\u00adti\u00adble, pro\u00advi\u00adding easy inte\u00adgra\u00adti\u00adon, and enables cus\u00adto\u00admers to dif\u00adfe\u00adren\u00adtia\u00adte their offe\u00adrings by pro\u00advi\u00adding indus\u00adtry-lea\u00adding per\u00adfor\u00admance while main\u00adtai\u00adning full com\u00adpa\u00adti\u00adbi\u00adli\u00adty with indus\u00adtry stan\u00addard <span class=\"caps\">DDR4<\/span>, and <span class=\"caps\">DDR3<\/span>\/<span class=\"caps\">3L<\/span>\/<span class=\"caps\">3U<\/span> inter\u00adfaces. Desi\u00adgned for fle\u00adxi\u00adbi\u00adli\u00adty, the R+ <span class=\"caps\">DDR4<\/span> <span class=\"caps\">PHY<\/span> deli\u00advers data rates from 800 to 3200 Mbps in mul\u00adti\u00adple memo\u00adry sub-sys\u00adtem opti\u00adons inclu\u00adding die down, <span class=\"caps\">DIMM<\/span>, and <span class=\"caps\">3DS<\/span>. In addi\u00adti\u00adon, the <span class=\"caps\">PHY<\/span> sup\u00adports 16 \u2013 72-bit inter\u00adfaces, along with sin\u00adgle and mul\u00adti-rank con\u00adfi\u00adgu\u00adra\u00adti\u00adons, allo\u00adwing the end cus\u00adto\u00admer to opti\u00admi\u00adze their design for per\u00adfor\u00admance, as well as both area and low&nbsp;power.<\/p>\n<p>For more infor\u00adma\u00adti\u00adon on R+ <span class=\"caps\">DDR4<\/span> and our other memo\u00adry PHYs, visit <a href=\"https:\/\/www.rambus.com\/memory-and-interfaces\/r-ddrn-phys\/\">rambus.com\/ddrnphys<\/a>.<\/p>\n<p><strong>Fol\u00adlow Rambus:<\/strong><br>\nCom\u00adpa\u00adny web\u00adsite: <a href=\"http:\/\/www.rambus.com\/\">rambus.com<\/a><br>\nRam\u00adbus blog: <a href=\"http:\/\/www.rambusblog.com\/\">rambusblog.com<\/a><br>\nTwit\u00adter: <a href=\"https:\/\/twitter.com\/rambusinc\">@rambusinc<\/a><br>\nLin\u00adke\u00addIn: <a href=\"http:\/\/www.linkedin.com\/company\/rambus\">www.linkedin.com\/company\/rambus<\/a><br>\nFace\u00adbook: <a href=\"http:\/\/www.facebook.com\/RambusInc\">www.facebook.com\/RambusInc<\/a><\/p>\n<p><strong>About Ram\u00adbus Memo\u00adry and Inter\u00adfaces Divi\u00adsi\u00adon (<span class=\"caps\">MID<\/span>)<\/strong><\/p>\n<p>The Ram\u00adbus Memo\u00adry and Inter\u00adfaces Divi\u00adsi\u00adon deve\u00adlo\u00adps pro\u00adducts and ser\u00advices that sol\u00adve the power, per\u00adfor\u00admance, and capa\u00adci\u00adty chal\u00adlenges of the mobi\u00adle, con\u00adnec\u00adted device, and cloud com\u00adpu\u00adting mar\u00adkets. Ram\u00adbus enhan\u00adced stan\u00addards-com\u00adpa\u00adti\u00adble and cus\u00adtom memo\u00adry and seri\u00adal link solu\u00adti\u00adons include chips, archi\u00adtec\u00adtures, memo\u00adry and chip-to-chip inter\u00adfaces, <span class=\"caps\">DRAM<\/span>, <span class=\"caps\">IP<\/span> vali\u00adda\u00adti\u00adon tools, and sys\u00adtem and <span class=\"caps\">IC<\/span> design ser\u00advices. Deve\u00adlo\u00adped through our sys\u00adtem-awa\u00adre design metho\u00addo\u00adlo\u00adgy, Ram\u00adbus pro\u00adducts deli\u00adver impro\u00adved time-to-mar\u00adket and first-time-right quality.<\/p>\n<p><strong>About Ram\u00adbus&nbsp;Inc.<\/strong><\/p>\n<p>Ram\u00adbus crea\u00adtes cut\u00adting-edge semi\u00adcon\u00adduc\u00adtor and <span class=\"caps\">IP<\/span> pro\u00adducts, span\u00adning memo\u00adry and inter\u00adfaces to secu\u00adri\u00adty, smart sen\u00adsors and light\u00ading. Our chips, cus\u00adto\u00admizable <span class=\"caps\">IP<\/span> cores, archi\u00adtec\u00adtu\u00adre licen\u00adses, soft\u00adware, tools, ser\u00advices, trai\u00adning and inno\u00adva\u00adtions impro\u00adve the com\u00adpe\u00adti\u00adti\u00adve advan\u00adta\u00adge of our cus\u00adto\u00admers. We col\u00adla\u00adbo\u00adra\u00adte with the indus\u00adtry, part\u00adne\u00adring with lea\u00adding <span class=\"caps\">ASIC<\/span> and SoC desi\u00adgners, found\u00adries, <span class=\"caps\">IP<\/span> deve\u00adlo\u00adpers, <span class=\"caps\">EDA<\/span> com\u00adpa\u00adnies and vali\u00adda\u00adti\u00adon labs. Our pro\u00adducts are inte\u00adgra\u00adted into tens of bil\u00adli\u00adons of devices and sys\u00adtems, powe\u00adring and secu\u00adring diver\u00adse appli\u00adca\u00adti\u00adons, inclu\u00adding Big Data, Inter\u00adnet of Things (IoT), mobi\u00adle, con\u00adsu\u00admer and media plat\u00adforms. At Ram\u00adbus, we are makers of bet\u00adter. For more infor\u00adma\u00adti\u00adon, visit<a href=\"http:\/\/www.rambus.com\/\">rambus.com<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Pro\u00adduc\u00adtion-rea\u00addy <span class=\"caps\">PHY<\/span> <span class=\"caps\">IP<\/span> will address the high-per\u00adfor\u00admance needs of enter\u00adpri\u00adse systems<\/p>\n<p><span class=\"caps\">SUNNYVALE<\/span>, Calif. \u2013 July 26, 2016 \u2013 Ram\u00adbus Inc. (<span class=\"caps\">NASDAQ<\/span>:<span class=\"caps\">RMBS<\/span>) today announ\u00adced that it has deve\u00adlo\u00adped an R+ <span class=\"caps\">DDR4<\/span> <span class=\"caps\">PHY<\/span> on the <span class=\"caps\">GLOBALFOUNDRIES<\/span> <span class=\"caps\">FX-14<\/span>\u2122 <span class=\"caps\">ASIC<\/span> plat\u00adform using the company\u2019s most advan\u00adced 14nm Power Plus (<span class=\"caps\">LPP<\/span>) pro\u00adcess. As part of a com\u00adpre\u00adhen\u00adsi\u00adve suite of memo\u00adry and Ser\u00adDes inter\u00adface offe\u00adrings for net\u00adwor\u00adking and data cen\u00adter appli\u00adca\u00adti\u00adons, Ram\u00adbus has achie\u00adved the first pro\u00adduc\u00adtion-rea\u00addy 3200 Mbps <span class=\"caps\">DDR4<\/span> <span class=\"caps\">PHY<\/span> available on <span class=\"caps\">GLOBALFOUNDRIES<\/span> power-per\u00adfor\u00admance opti\u00admi\u00adzed 14nm <span class=\"caps\">LPP<\/span> pro\u00adcess. The R+ <span class=\"caps\">DDR4<\/span> <span class=\"caps\">PHY<\/span> is desi\u00adgned to meet the per\u00adfor\u00admance and capa\u00adci\u00adty demands of the next wave of data cen\u00adter and net\u00adwor\u00adking mar\u00adkets. (\u2026) <a class=\"moretag\" href=\"https:\/\/www.planet3dnow.de\/cms\/26005-rambus-announces-silicon-proven-r-ddr4-phy-on-globalfoundries-14nm-lpp-process-for-networking-and-data-center-applications\/\">Wei\u00adter\u00adle\u00adsen&nbsp;\u00bb<\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[],"class_list":["post-26005","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/26005","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=26005"}],"version-history":[{"count":1,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/26005\/revisions"}],"predecessor-version":[{"id":26006,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/26005\/revisions\/26006"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=26005"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=26005"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=26005"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}