{"id":32073,"date":"2017-05-26T08:26:52","date_gmt":"2017-05-26T06:26:52","guid":{"rendered":"http:\/\/www.planet3dnow.de\/cms\/?p=32073"},"modified":"2017-05-26T17:23:49","modified_gmt":"2017-05-26T15:23:49","slug":"agesa-1-0-0-6-mit-verbesserungen-bei-ram-stabilitaet-virtualisierung-und-flexibilitaet","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/32073-agesa-1-0-0-6-mit-verbesserungen-bei-ram-stabilitaet-virtualisierung-und-flexibilitaet\/","title":{"rendered":"AGESA<\/span> 1.0.0.6 mit Verbesserungen bei DRAM<\/span>, Virtualisierung und Flexibilit\u00e4t"},"content":{"rendered":"

In sei\u00adnem Blog<\/a> hat AMD<\/span> einen Aus\u00adblick auf das AGE\u00adSA-Update 1.0.0.6 gew\u00e4hrt. AGESA<\/span> steht f\u00fcr AMD<\/span> Gene\u00adric Encap\u00adsu\u00adla\u00adted Sys\u00adtem Archi\u00adtec\u00adtu\u00adre und bil\u00addet das Grund\u00adge\u00adr\u00fcst zur Initia\u00adli\u00adsie\u00adrung von AMD-Pro\u00adzes\u00adso\u00adren in der Pha\u00adse des Power-On-Self-Test (POST<\/span>) nach dem Ein\u00adschal\u00adten des Sys\u00adtems. Dar\u00adauf basie\u00adrend ent\u00adwi\u00adckeln die Main\u00adboard-Her\u00adstel\u00adler ihre Firm\u00adware (ali\u00adas BIOS<\/span> ali\u00adas UEFI<\/span>).<\/p>\n

Wie bereits in einem fr\u00fc\u00adhe\u00adren Blog\u00adbei\u00adtrag ver\u00adra\u00adten, will AMD<\/span> mit dem Update 1.0.0.6 die hohen DRAM-Over\u00adclo\u00adcking-Fre\u00adquen\u00adzen ange\u00adhen. Mit Over\u00adclo\u00adcking meint AMD<\/span> alles \u00fcber DDR4-2667<\/span>, der h\u00f6chs\u00adten offi\u00adzi\u00adell f\u00fcr Ryzen frei\u00adge\u00adge\u00adbe\u00adnen Spei\u00adcher\u00adtakt\u00adra\u00adte. So sol\u00adlen k\u00fcnf\u00adtig auch Fre\u00adquen\u00adzen \u00fcber 3200 MHz ein\u00adstell\u00adbar und vor allem sta\u00adbil nutz\u00adbar sein, denn dass Ryzen eine zicki\u00adge Diva in Sachen Spei\u00adcher\u00adkom\u00adpa\u00adti\u00adbi\u00adli\u00adt\u00e4t sein kann, haben wir ja schon mehr\u00adfach the\u00adma\u00adti\u00adsiert<\/a>.<\/p>\n

Doch das AGE\u00adSA-Update 1.0.0.6 soll noch wei\u00adte\u00adre Fea\u00adtures frei\u00adschal\u00adten. So soll es mit IOMMU<\/span> Groups m\u00f6g\u00adlich sein, Vir\u00adtu\u00adel\u00adlen Maschi\u00adnen ein\u00adzel\u00adne Gra\u00adfik\u00adkar\u00adten zuzuweisen:<\/p>\n

This capa\u00adbi\u00adli\u00adty is espe\u00adci\u00adal\u00adly useful for users that want 3D-acce\u00adle\u00adra\u00adted gra\u00adphics insi\u00adde a vir\u00adtu\u00adal machi\u00adne. With ACS<\/span> sup\u00adport, it is pos\u00adsi\u00adble to split a 2\u2011GPU<\/span> sys\u00adtem such that a host Linux\u00ae OS<\/span> and a Win\u00addows VM<\/span> both have a dedi\u00adca\u00adted gra\u00adphics cards. The vir\u00adtu\u00adal machi\u00adne can access all the capa\u00adbi\u00adli\u00adties of the dedi\u00adca\u00adted GPU<\/span>, and run games insi\u00adde the vir\u00adtu\u00adal machi\u00adne at near-nati\u00adve performance.<\/p><\/blockquote>\n

Abge\u00adse\u00adhen davon ver\u00adspricht AMD<\/span> 26 neue Fea\u00adtures, dar\u00adun\u00adter end\u00adlich die manu\u00adel\u00adle Kon\u00adfi\u00adgu\u00adrier\u00adbar\u00adkeit der DRAM<\/span> Com\u00admand Rate.<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Para\u00adme\u00adter<\/strong><\/th>\nFunc\u00adtion<\/strong><\/th>\nValues<\/strong><\/th>\n<\/tr>\n<\/thead>\n
tWTR_S<\/td>\nWri\u00adte to read delay (short), or the time bet\u00adween a wri\u00adte tran\u00adsac\u00adtion and read com\u00admand on a dif\u00adfe\u00adrent bank group.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tWTR_L<\/td>\nWri\u00adte to read delay (long), or the time bet\u00adween a wri\u00adte tran\u00adsac\u00adtion and read com\u00admand on the same bank group.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tWR<\/td>\nWri\u00adte reco\u00advery time, or the time that must elap\u00adse bet\u00adween a valid wri\u00adte ope\u00adra\u00adti\u00adon and the prech\u00adar\u00adging of ano\u00adther bank. Hig\u00adher values are often bene\u00adfi\u00adci\u00adal for sta\u00adbi\u00adli\u00adty, and values < 8 can quick\u00adly cor\u00adrupt data stored in RAM<\/span>.<\/td>\nInte\u00adger values (ns)<\/td>\n<\/tr>\n
tWR<\/td>\nWri\u00adte reco\u00advery time, or the time that must elap\u00adse bet\u00adween a valid wri\u00adte ope\u00adra\u00adti\u00adon and the prech\u00adar\u00adging of ano\u00adther bank. Hig\u00adher values are often bet\u00adter for stability.<\/td>\nInte\u00adger values (ns)<\/td>\n<\/tr>\n
tWCL\/tWL\/tCWL<\/td>\nCAS<\/span> Wri\u00adte Laten\u00adcy, or the amount of time it takes to wri\u00adte to the open memo\u00adry bank. WCL<\/span> is gene\u00adral\u00adly con\u00adfi\u00adgu\u00adred equal to CAS<\/span> or CAS<\/span>\u20111. This can be a signi\u00adfi\u00adcant timing for sta\u00adbi\u00adli\u00adty, and lower values often pro\u00adve better.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tRTP<\/td>\nRead to prech\u00adar\u00adge time, or the num\u00adber of clock cycles bet\u00adween a READ<\/span> com\u00admand to a row and a prech\u00adar\u00adge com\u00admand to the same rank.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tRRD_S<\/td>\nActi\u00adva\u00adte to acti\u00adva\u00adte delay (short), or the num\u00adber of clock cycles bet\u00adween acti\u00adva\u00adte com\u00admands in a dif\u00adfe\u00adrent bank group.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tRRD_L<\/td>\nActi\u00adva\u00adte to acti\u00adva\u00adte delay (long), or the num\u00adber of clock cycles bet\u00adween acti\u00adva\u00adte com\u00admands in the same bank group.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tRFC4<\/td>\nRefresh cycle time for quad fre\u00adquen\u00adcy (4x) mode. This is typi\u00adcal\u00adly a timing auto\u00adma\u00adti\u00adcal\u00adly deri\u00adved from other values.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tRFC2<\/td>\nRefresh cycle time for dou\u00adble fre\u00adquen\u00adcy (2x) mode.  This is typi\u00adcal\u00adly a timing auto\u00adma\u00adti\u00adcal\u00adly deri\u00adved from other values.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tRFC<\/td>\nRefresh cycle time, or the time it takes for the memo\u00adry to read and re-wri\u00adte infor\u00adma\u00adti\u00adon to the same DRAM<\/span> cell for the pur\u00adpo\u00adses of pre\u00adser\u00adving infor\u00adma\u00adti\u00adon. This is typi\u00adcal\u00adly a timing auto\u00adma\u00adti\u00adcal\u00adly deri\u00adved from other values.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tRD\u00adWR \/ tWRRD<\/td>\nRead-to-wri\u00adte and wri\u00adte-to-read laten\u00adcy, or the time that must elap\u00adse bet\u00adween issuing sequen\u00adti\u00adal read\/write or write\/read commands.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tRDRD \/ tWRWR<\/td>\nRead-to-read and wri\u00adte-to-wri\u00adte laten\u00adcy, or the time bet\u00adween sequen\u00adti\u00adal read or wri\u00adte requests (e.g. DIMM-to-DIMM, or across ranks). Lower values can signi\u00adfi\u00adcant\u00adly impro\u00adve DRAM<\/span> through\u00adput, but high memo\u00adry clocks often demand rela\u00adxed timings.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tRC<\/td>\nRow cycle time, or the num\u00adber of clock cycles requi\u00adred for a memo\u00adry row to com\u00adple\u00adte a full ope\u00adra\u00adtio\u00adnal cycle. Lower values can nota\u00adb\u00adly impro\u00adve per\u00adfor\u00admance<\/a>, but should not be set lower than tRP+tRAS for sta\u00adbi\u00adli\u00adty reasons.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tMAW<\/td>\nMaxi\u00admum acti\u00adva\u00adti\u00adon win\u00addow, or the maxi\u00admum num\u00adber of times a DRAM<\/span> row can be acti\u00adva\u00adted befo\u00adre adja\u00adcent memo\u00adry rows must be refres\u00adhed to pre\u00adser\u00adve data.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tMAC<\/td>\nMaxi\u00admum acti\u00adva\u00adte count, or the num\u00adber of times a row is acti\u00adva\u00adted by the sys\u00adtem befo\u00adre adja\u00adcent row refresh. Must be equal to or less than tMAW.<\/td>\nInte\u00adger values (cycles)<\/td>\n<\/tr>\n
tFAW<\/td>\nFour acti\u00adva\u00adti\u00adon win\u00addow, or the time that must elap\u00adse befo\u00adre new memo\u00adry banks can be acti\u00adva\u00adted after four ACTIVATE<\/span> com\u00admands have been issued. Con\u00adfi\u00adgu\u00adred to a min\u00adu\u00admum 4x tRRD_S, but values >8x tRRD_S are often used for stability.<\/td>\nInte\u00adger values (ns)<\/td>\n<\/tr>\n
Rtt<\/td>\nCon\u00adtrols the per\u00adfor\u00admance of DRAM<\/span> inter\u00adnal ter\u00admi\u00adna\u00adti\u00adon resis\u00adtors during nomi\u00adnal, wri\u00adte, and park states.<\/td>\nNom(inal), WR<\/span>(ite), and Park inte\u00adgers (ohms)<\/td>\n<\/tr>\n
Pro\u00adcODT (CPU<\/span> on-die termination)<\/td>\nA resis\u00adtance value, in ohms, that deter\u00admi\u00adnes how a com\u00adple\u00adted memo\u00adry signal is ter\u00admi\u00adna\u00adted. Hig\u00adher values can help sta\u00adbi\u00adli\u00adze hig\u00adher data rates. Values in the ran\u00adge of 60\u201396 can pro\u00adve helpful.<\/td>\nInte\u00adger values (ohms)<\/td>\n<\/tr>\n
Memo\u00adry clocks<\/td>\nAdded divi\u00adders for memo\u00adry clocks up to DDR4-4000<\/span> wit\u00adhout ref\u00adclk adjus\u00adt\u00adment. Plea\u00adse note that values grea\u00adter than DDR4-2667<\/span> is over\u00adclo\u00adcking<\/strong>. Your mileage may vary (as noted by our big over\u00adclo\u00adcking wart\u00adning at the end of this blog).<\/td>\n133.33MT<\/span>\/s inter\u00advals (2667, 2933, 3067, 3200, 3333, 3466, 3600, 3733, 3866, 4000)<\/td>\n<\/tr>\n
Gear\u00addown Mode<\/td>\nAllows the DRAM<\/span> device to run off its intern\u00adal\u00adly-gene\u00adra\u00adted \u00bd rate clock for lat\u00adching on the com\u00admand or address buses. ON<\/span> is the default for speeds grea\u00adter than DDR4-2667<\/span>, howe\u00adver the bene\u00adfit of ON<\/span> vs. OFF<\/span> will vary from memo\u00adry kit to memo\u00adry kit. Enab\u00adling Gear\u00addown Mode will over\u00adri\u00adde your cur\u00adrent com\u00admand rate.<\/td>\nOn\/Off<\/td>\n<\/tr>\n
DRAM<\/span> Power Down<\/td>\nCan mode\u00adst\u00adly save sys\u00adtem power, at the expen\u00adse of hig\u00adher DRAM<\/span> laten\u00adcy, by put\u00adting DRAM<\/span> into a quie\u00ads\u00adcent sta\u00adte after a peri\u00adod of inactivity.<\/td>\nOn\/Off<\/td>\n<\/tr>\n
Com\u00admand rate (CR<\/span>)<\/td>\nThe amount of time, in cycles, bet\u00adween when a DRAM<\/span> chip is sel\u00adec\u00adted and a com\u00admand is exe\u00adcu\u00adted. 2T<\/span> CR<\/span> can be very bene\u00adfi\u00adci\u00adal for sta\u00adbi\u00adli\u00adty with high memo\u00adry clocks, or for 4\u2011DIMM<\/span> configurations.<\/td>\n2T<\/span>, 1T<\/span><\/td>\n<\/tr>\n
CLDO_VDDP<\/span><\/td>\nVol\u00adta\u00adge for the DDR4<\/span> PHY<\/span> on the SoC. Some\u00adwhat coun\u00adter\u00adin\u00adtui\u00adtively, lowe\u00adring VDDP<\/span> can often be more bene\u00adfi\u00adci\u00adal for sta\u00adbi\u00adli\u00adty than rai\u00adsing CLDO_VDDP<\/span>. Advan\u00adced over\u00adclo\u00adckers should also know that alte\u00adring CLDO_VDDP<\/span> can move or resol\u00adve memo\u00adry holes. Small chan\u00adges to VDDP<\/span> can have a big effect, and VDDP<\/span> should not be set to a value grea\u00adter than VDIMM<\/span>\u20110.1V<\/span>. A cold reboot is requi\u00adred if you alter this voltage.\n

 <\/p>\n

Siden\u00adote:<\/strong> pre\u20111.0.0.6 BIO\u00adSes may also have an ent\u00adry labe\u00adled \u201cVDDP<\/span>\u201d that alters the exter\u00adnal vol\u00adta\u00adge level sent to the CPU<\/span> VDDP<\/span> pins. This is not the same para\u00adme\u00adter as CLDO_VDDP<\/span> in AGESA<\/span> 1.0.0.6.<\/p><\/td>\n

Inte\u00adger values<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

In sei\u00adnem Blog hat AMD<\/span> einen Aus\u00adblick auf das AGE\u00adSA-Update 1.0.0.6 gew\u00e4hrt. AGESA<\/span> steht f\u00fcr AMD<\/span> Gene\u00adric Encap\u00adsu\u00adla\u00adted Sys\u00adtem Archi\u00adtec\u00adtu\u00adre und bil\u00addet das Grund\u00adge\u00adr\u00fcst zur Initia\u00adli\u00adsie\u00adrung von AMD-Pro\u00adzes\u00adso\u00adren in der Pha\u00adse des Power-On-Self-Test (POST<\/span>) nach dem Ein\u00adschal\u00adten des Sys\u00adtems. Dar\u00adauf basie\u00adrend ent\u00adwi\u00adckeln die Main\u00adboard-Her\u00adstel\u00adler ihre Firm\u00adware (BIOS<\/span>\/UEFI<\/span>). (\u2026) Wei\u00adter\u00adle\u00adsen \u00bb<\/a><\/p>\n","protected":false},"author":2,"featured_media":29295,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[12],"tags":[1265,833,1210],"class_list":["post-32073","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-aktuelles","tag-agesa","tag-am4","tag-ryzen","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/32073","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=32073"}],"version-history":[{"count":8,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/32073\/revisions"}],"predecessor-version":[{"id":32099,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/32073\/revisions\/32099"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media\/29295"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=32073"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=32073"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=32073"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}