{"id":42494,"date":"2018-12-12T16:20:05","date_gmt":"2018-12-12T15:20:05","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=42494"},"modified":"2018-12-12T16:20:05","modified_gmt":"2018-12-12T15:20:05","slug":"new-intel-architectures-and-technologies-target-expanded-market-opportunities","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/42494-new-intel-architectures-and-technologies-target-expanded-market-opportunities\/","title":{"rendered":"New Intel Architectures and Technologies Target Expanded Market Opportunities"},"content":{"rendered":"<p><span class=\"caps\">SANTA<\/span> <span class=\"caps\">CLARA<\/span>, Calif., Dec. 12, 2018 \u2013 At Intel \u201cArchi\u00adtec\u00adtu\u00adre Day,\u201d top exe\u00adcu\u00adti\u00adves, archi\u00adtects and fel\u00adlows reve\u00ada\u00adled next-gene\u00adra\u00adti\u00adon tech\u00adno\u00adlo\u00adgies and dis\u00adcus\u00adsed pro\u00adgress on a stra\u00adtegy to power an expan\u00adding uni\u00adver\u00adse of data-inten\u00adsi\u00adve workloads for PCs and other smart con\u00adsu\u00admer devices, high-speed net\u00adworks, ubi\u00adqui\u00adtous arti\u00adfi\u00adci\u00adal intel\u00adli\u00adgence (<span class=\"caps\">AI<\/span>), spe\u00adcia\u00adli\u00adzed cloud data cen\u00adters and auto\u00adno\u00admous vehicles.<\/p>\n<p>Intel demons\u00adtra\u00adted a ran\u00adge of 10nm-based sys\u00adtems in deve\u00adlo\u00adp\u00adment for PCs, data cen\u00adters and net\u00adwor\u00adking, and pre\u00adview\u00aded other tech\u00adno\u00adlo\u00adgies tar\u00adge\u00adted at an expan\u00added ran\u00adge of workloads.<\/p>\n<p><strong>More:&nbsp;<\/strong><a href=\"https:\/\/newsroom.intel.com\/news\/new-intel-architectures-technologies-target-expanded-market-opportunities\/\">New Intel Archi\u00adtec\u00adtures and Tech\u00adno\u00adlo\u00adgies Tar\u00adget Expan\u00added Mar\u00adket Opportunities<\/a><\/p>\n<p><span style=\"font-size: 1rem;\"><br>\nTog\u00ade\u00adther the\u00adse tech\u00adno\u00adlo\u00adgies lay the foun\u00adda\u00adti\u00adon for a more diver\u00adse era of com\u00adpu\u00adting in an expan\u00added addressa\u00adble mar\u00adket oppor\u00adtu\u00adni\u00adty of more than $300 bil\u00adli\u00adon by 2022.<\/span><sup>1<\/sup>The com\u00adpa\u00adny also shared its tech\u00adni\u00adcal stra\u00adtegy focu\u00adsed on six engi\u00adnee\u00adring seg\u00adments whe\u00adre signi\u00adfi\u00adcant invest\u00adments and inno\u00adva\u00adti\u00adon are being pur\u00adsued to dri\u00adve leaps for\u00adward in tech\u00adno\u00adlo\u00adgy and user expe\u00adri\u00adence. They include: advan\u00adced manu\u00adfac\u00adtu\u00adring pro\u00adces\u00adses and pack\u00ada\u00adging; new archi\u00adtec\u00adtures to speed-up spe\u00adcia\u00adli\u00adzed tasks like <span class=\"caps\">AI<\/span> and gra\u00adphics; super-fast memo\u00adry; inter\u00adcon\u00adnects; embedded secu\u00adri\u00adty fea\u00adtures; and com\u00admon soft\u00adware to uni\u00adfy and sim\u00adpli\u00adfy pro\u00adgramming for deve\u00adlo\u00adpers across Intel\u2019s com\u00adpu\u00adte roadmap.<\/p>\n<p style=\"text-align: center;\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter\" src=\"https:\/\/newsroom.intel.com\/wp-content\/uploads\/sites\/11\/2018\/12\/2d-and-3d-packaging-drive-new-design-flexibility.jpg\" alt width=\"436\" height=\"270\"><\/p>\n<p>&nbsp;<\/p>\n<p>Intel Archi\u00adtec\u00adtu\u00adre Day Highlights:<\/p>\n<ul>\n<li><strong>Indus\u00adtry-First <span class=\"caps\">3D<\/span> Stack\u00ading of Logic Chips:&nbsp;<\/strong>Intel demons\u00adtra\u00adted a new <span class=\"caps\">3D<\/span> pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgy, cal\u00adled \u201cFove\u00adr\u00ados,\u201d which for the first time brings the bene\u00adfits of <span class=\"caps\">3D<\/span> stack\u00ading to enable logic-on-logic integration.<br>\n&nbsp;<br>\nFove\u00adr\u00ados paves the way for devices and sys\u00adtems com\u00adbi\u00adning high-per\u00adfor\u00admance, high-den\u00adsi\u00adty and low-power sili\u00adcon pro\u00adcess tech\u00adno\u00adlo\u00adgies. Fove\u00adr\u00ados is expec\u00adted to extend die stack\u00ading bey\u00adond tra\u00addi\u00adtio\u00adnal pas\u00adsi\u00adve inter\u00adpo\u00adsers and sta\u00adcked memo\u00adry to high-per\u00adfor\u00admance logic, such as <span class=\"caps\">CPU<\/span>, gra\u00adphics and <span class=\"caps\">AI<\/span> pro\u00adces\u00adsors for the first&nbsp;time.<br>\n&nbsp;<br>\nThe tech\u00adno\u00adlo\u00adgy pro\u00advi\u00addes tre\u00admen\u00addous fle\u00adxi\u00adbi\u00adli\u00adty as desi\u00adgners seek to \u201cmix and match\u201d tech\u00adno\u00adlo\u00adgy <span class=\"caps\">IP<\/span> blocks with various memo\u00adry and I\/O ele\u00adments in new device form fac\u00adtors. It will allow pro\u00adducts to be bro\u00adken up into smal\u00adler \u201cchip\u00adlets,\u201d whe\u00adre I\/O, <span class=\"caps\">SRAM<\/span> and power deli\u00advery cir\u00adcuits can be fabri\u00adca\u00adted in a base die and high-per\u00adfor\u00admance logic chip\u00adlets are sta\u00adcked on&nbsp;top.<br>\n&nbsp;<br>\nIntel expects to launch a ran\u00adge of pro\u00adducts using Fove\u00adr\u00ados begin\u00adning in the second half of 2019. The first Fove\u00adr\u00ados pro\u00adduct will com\u00adbi\u00adne a high-per\u00adfor\u00admance 10nm com\u00adpu\u00adte-sta\u00adcked chip\u00adlet with a low-power <span class=\"caps\">22FFL<\/span> base die. It will enable the com\u00adbi\u00adna\u00adti\u00adon of world-class per\u00adfor\u00admance and power effi\u00adci\u00aden\u00adcy in a small form factor.<br>\n&nbsp;<br>\nFove\u00adr\u00ados is the next leap for\u00adward fol\u00adlo\u00adwing Intel\u2019s breakth\u00adrough Embedded Mul\u00adti-die Inter\u00adcon\u00adnect Bridge (<span class=\"caps\">EMIB<\/span>) <span class=\"caps\">2D<\/span> pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgy, intro\u00addu\u00adced in&nbsp;2018.<br>\n&nbsp;<\/li>\n<li><strong>New Sun\u00adny Cove <span class=\"caps\">CPU<\/span> Archi\u00adtec\u00adtu\u00adre:<\/strong>&nbsp;Intel intro\u00addu\u00adced Sun\u00adny Cove, Intel\u2019s next-gene\u00adra\u00adti\u00adon <span class=\"caps\">CPU<\/span> micro\u00adar\u00adchi\u00adtec\u00adtu\u00adre desi\u00adgned to increase per\u00adfor\u00admance per clock and power effi\u00adci\u00aden\u00adcy for gene\u00adral pur\u00adpo\u00adse com\u00adpu\u00adting tasks, and includes new fea\u00adtures to acce\u00adle\u00adra\u00adte spe\u00adcial pur\u00adpo\u00adse com\u00adpu\u00adting tasks like <span class=\"caps\">AI<\/span> and cryp\u00adto\u00adgra\u00adphy. Sun\u00adny Cove will be the basis for Intel\u2019s next-gene\u00adra\u00adti\u00adon ser\u00adver (Intel\u00ae Xeon\u00ae) and cli\u00adent (Intel\u00ae Core\u2122) pro\u00adces\u00adsors later next year. Sun\u00adny Cove fea\u00adtures include:<br>\n&nbsp;\n<ul>\n<li>Enhan\u00adced micro\u00adar\u00adchi\u00adtec\u00adtu\u00adre to exe\u00adcu\u00adte more ope\u00adra\u00adti\u00adons in parallel.<\/li>\n<li>New algo\u00adrith\u00adms to redu\u00adce latency.<\/li>\n<li>Increased size of key buf\u00adfers and caches to opti\u00admi\u00adze data-cen\u00adtric workloads.<\/li>\n<li>Archi\u00adtec\u00adtu\u00adral exten\u00adsi\u00adons for spe\u00adci\u00adfic use cases and algo\u00adrith\u00adms. For exam\u00adp\u00adle, new per\u00adfor\u00admance-boos\u00adting ins\u00adtruc\u00adtions for cryp\u00adto\u00adgra\u00adphy, such as vec\u00adtor <span class=\"caps\">AES<\/span> and <span class=\"caps\">SHA-NI<\/span>, and other cri\u00adti\u00adcal use cases like com\u00adpres\u00adsi\u00adon and decompression.<\/li>\n<\/ul>\n<p>&nbsp;<br>\nSun\u00adny Cove enables redu\u00adced laten\u00adcy and high through\u00adput, as well as offers much grea\u00adter par\u00adal\u00adle\u00adlism that is expec\u00adted to impro\u00adve expe\u00adri\u00aden\u00adces from gam\u00ading to media to data-cen\u00adtric applications.<\/p><\/li>\n<li><strong>Next-Gene\u00adra\u00adti\u00adon Gra\u00adphics:<\/strong>&nbsp;Intel unvei\u00adled new Gen11 inte\u00adgra\u00adted gra\u00adphics with 64 enhan\u00adced exe\u00adcu\u00adti\u00adon units, more than dou\u00adble pre\u00advious Intel Gen9 gra\u00adphics (24 EUs), desi\u00adgned to break the 1 <span class=\"caps\">TFLOPS<\/span> bar\u00adri\u00ader. The new inte\u00adgra\u00adted gra\u00adphics will be deli\u00adver\u00aded in 10nm-based pro\u00adces\u00adsors begin\u00adning in&nbsp;2019.<br>\n&nbsp;<br>\nThe new inte\u00adgra\u00adted gra\u00adphics archi\u00adtec\u00adtu\u00adre is expec\u00adted to dou\u00adble the com\u00adpu\u00adting per\u00adfor\u00admance-per-clock com\u00adpared to Intel Gen9 gra\u00adphics. With &gt;1 <span class=\"caps\">TFLOPS<\/span> per\u00adfor\u00admance capa\u00adbi\u00adli\u00adty, this archi\u00adtec\u00adtu\u00adre is desi\u00adgned to increase game playa\u00adbi\u00adli\u00adty. At the event, Intel show\u00aded Gen11 gra\u00adphics near\u00adly doubling the per\u00adfor\u00admance of a popu\u00adlar pho\u00adto reco\u00adgni\u00adti\u00adon appli\u00adca\u00adti\u00adon when com\u00adpared to Intel\u2019s Gen9 gra\u00adphics. Gen11 gra\u00adphics is expec\u00adted to also fea\u00adture an advan\u00adced media enco\u00adder and deco\u00adder, sup\u00adport\u00ading <span class=\"caps\">4K<\/span> video streams and <span class=\"caps\">8K<\/span> con\u00adtent crea\u00adti\u00adon in cons\u00adtrai\u00adned power enve\u00adlo\u00adpes. Gen11 will also fea\u00adture Intel\u00ae Adap\u00adti\u00adve Sync tech\u00adno\u00adlo\u00adgy enab\u00adling smooth frame rates for gaming.<br>\n&nbsp;<br>\nIntel also reaf\u00adfirm\u00aded its plan to intro\u00addu\u00adce a dis\u00adcrete gra\u00adphics pro\u00adces\u00adsor by&nbsp;2020.<\/li>\n<li><strong><span class=\"dquo\">\u201c<\/span>One <span class=\"caps\">API<\/span>\u201d Soft\u00adware:<\/strong>&nbsp;Intel announ\u00adced the \u201cOne <span class=\"caps\">API<\/span>\u201d pro\u00adject to sim\u00adpli\u00adfy the pro\u00adgramming of diver\u00adse com\u00adpu\u00adting engi\u00adnes across <span class=\"caps\">CPU<\/span>, <span class=\"caps\">GPU<\/span>, <span class=\"caps\">FPGA<\/span>, <span class=\"caps\">AI<\/span> and other acce\u00adle\u00adra\u00adtors. The pro\u00adject includes a com\u00adpre\u00adhen\u00adsi\u00adve and uni\u00adfied port\u00adfo\u00adlio of deve\u00adlo\u00adper tools for map\u00adping soft\u00adware to the hard\u00adware that can best acce\u00adle\u00adra\u00adte the code. A public pro\u00adject release is expec\u00adted to be available in&nbsp;2019.<\/li>\n<li><strong>Memo\u00adry and Sto\u00adrage:&nbsp;<\/strong>Intel dis\u00adcus\u00adsed updates on Intel\u00ae Opta\u00adne\u2122 tech\u00adno\u00adlo\u00adgy and the pro\u00adducts based upon that tech\u00adno\u00adlo\u00adgy. Intel\u00ae Opta\u00adne\u2122 <span class=\"caps\">DC<\/span> per\u00adsis\u00adtent memo\u00adry is a new pro\u00adduct that con\u00adver\u00adges memo\u00adry-like per\u00adfor\u00admance with the data per\u00adsis\u00adtence and lar\u00adge capa\u00adci\u00adty of sto\u00adrage. The revo\u00adlu\u00adtio\u00adna\u00adry tech\u00adno\u00adlo\u00adgy brings more data clo\u00adser to the <span class=\"caps\">CPU<\/span> for fas\u00adter pro\u00adces\u00adsing of big\u00adger data sets like tho\u00adse used in <span class=\"caps\">AI<\/span> and lar\u00adge data\u00adba\u00adses. Its lar\u00adge capa\u00adci\u00adty and data per\u00adsis\u00adtence redu\u00adces the need to make time-con\u00adsum\u00ading trips to sto\u00adrage, which can impro\u00adve workload per\u00adfor\u00admance. Intel Opta\u00adne <span class=\"caps\">DC<\/span> per\u00adsis\u00adtent memo\u00adry deli\u00advers cache line (<span class=\"caps\">64B<\/span>) reads to the <span class=\"caps\">CPU<\/span>. On avera\u00adge, the avera\u00adge idle read laten\u00adcy with Opta\u00adne per\u00adsis\u00adtent memo\u00adry is expec\u00adted to be about 350 nano\u00adse\u00adconds when appli\u00adca\u00adti\u00adons direct the read ope\u00adra\u00adti\u00adon to Opta\u00adne per\u00adsis\u00adtent memo\u00adry, or when the reques\u00adted data is not cached in <span class=\"caps\">DRAM<\/span>. For sca\u00adle, an Opta\u00adne <span class=\"caps\">DC<\/span> <span class=\"caps\">SSD<\/span> has an avera\u00adge idle read laten\u00adcy of about 10,000 nano\u00adse\u00adconds (10 micro\u00adse\u00adconds), a remar\u00adkab\u00adle impro\u00adve\u00adment.<sup>2<\/sup>&nbsp;In cases whe\u00adre reques\u00adted data is in <span class=\"caps\">DRAM<\/span>, eit\u00adher cached by the <span class=\"caps\">CPU<\/span>\u2019s memo\u00adry con\u00adtrol\u00adler or direc\u00adted by the appli\u00adca\u00adti\u00adon, memo\u00adry sub-sys\u00adtem respon\u00adsi\u00adve\u00adness is expec\u00adted to be iden\u00adti\u00adcal to <span class=\"caps\">DRAM<\/span> (&lt;100 nanoseconds).<\/li>\n<\/ul>\n<p>The com\u00adpa\u00adny also show\u00aded how SSDs based on Intel\u2019s 1 Tera\u00adbit <span class=\"caps\">QLC<\/span> <span class=\"caps\">NAND<\/span> die move more bulk data from HDDs to SSDs, allo\u00adwing fas\u00adter access to that&nbsp;data.<br>\n&nbsp;<br>\nThe com\u00adbi\u00adna\u00adti\u00adon of Intel Opta\u00adne SSDs with <span class=\"caps\">QLC<\/span> <span class=\"caps\">NAND<\/span> SSDs will enable lower laten\u00adcy access to data used most fre\u00adquent\u00adly. Taken tog\u00ade\u00adther, the\u00adse plat\u00adform and memo\u00adry advan\u00adces com\u00adple\u00adte the memo\u00adry and sto\u00adrage hier\u00adar\u00adchy pro\u00advi\u00adding the right set of choices for sys\u00adtems and applications.<\/p>\n<ul>\n<li><strong>Deep Lear\u00adning Refe\u00adrence Stack:&nbsp;<\/strong>Intel is releasing the Deep Lear\u00adning Refe\u00adrence Stack, an inte\u00adgra\u00adted, high\u00adly-per\u00adfor\u00admant open source stack opti\u00admi\u00adzed for Intel\u00ae Xeon\u00ae Sca\u00adlable plat\u00adforms. This open source com\u00admu\u00adni\u00adty release is part of our effort to ensu\u00adre <span class=\"caps\">AI<\/span> deve\u00adlo\u00adpers have easy access to all of the fea\u00adtures and func\u00adtion\u00ada\u00adli\u00adty of the Intel plat\u00adforms. The Deep Lear\u00adning Refe\u00adrence Stack is high\u00adly-tun\u00aded and built for cloud nati\u00adve envi\u00adron\u00adments. With this release, Intel is enab\u00adling deve\u00adlo\u00adpers to quick\u00adly pro\u00adto\u00adty\u00adpe by redu\u00adcing the com\u00adple\u00adxi\u00adty asso\u00adcia\u00adted with inte\u00adgra\u00adting mul\u00adti\u00adple soft\u00adware com\u00adpon\u00adents, while still giving users the fle\u00adxi\u00adbi\u00adli\u00adty to cus\u00adto\u00admi\u00adze their solutions.<\/li>\n<li>\n<ul>\n<li><strong>Ope\u00adra\u00adting Sys\u00adtem:&nbsp;<\/strong>Clear Linux* <span class=\"caps\">OS<\/span> is cus\u00adto\u00admizable to indi\u00advi\u00addu\u00adal deve\u00adlo\u00adp\u00adment needs, tun\u00aded for Intel plat\u00adforms and spe\u00adci\u00adfic use cases like deep learning;<\/li>\n<li><strong>Orchestra\u00adti\u00adon:&nbsp;<\/strong>Kuber\u00adnetes* mana\u00adges and orchestra\u00adtes con\u00adtai\u00adne\u00adri\u00adzed appli\u00adca\u00adti\u00adons for mul\u00adti-node clus\u00adters with Intel plat\u00adform awareness;<\/li>\n<li><strong>Con\u00adtai\u00adners:&nbsp;<\/strong>Docker* con\u00adtai\u00adners and Kata* con\u00adtai\u00adners uti\u00adli\u00adze Intel\u00ae Vir\u00adtua\u00adliza\u00adti\u00adon Tech\u00adno\u00adlo\u00adgy to help secu\u00adre container;<\/li>\n<li><strong>Libra\u00adri\u00ades:&nbsp;<\/strong>Intel\u00ae Math Ker\u00adnel Libra\u00adry for Deep Neu\u00adral Net\u00adworks (<span class=\"caps\">MKL<\/span> <span class=\"caps\">DNN<\/span>) is Intel\u2019s high\u00adly opti\u00admi\u00adzed math libra\u00adry for mathe\u00adma\u00adti\u00adcal func\u00adtion performance;<\/li>\n<li><strong>Run\u00adtimes:&nbsp;<\/strong>Python* pro\u00advi\u00adding appli\u00adca\u00adti\u00adon and ser\u00advice exe\u00adcu\u00adti\u00adon run\u00adtime sup\u00adport is high\u00adly tun\u00aded and opti\u00admi\u00adzed for Intel architecture;<\/li>\n<li><strong>Frame\u00adworks:<\/strong>&nbsp;Ten\u00adsor\u00adFlow* is a lea\u00adding deep lear\u00adning and machi\u00adne lear\u00adning framework;<\/li>\n<li><strong>Deploy\u00adment:&nbsp;<\/strong>Kube\u00adFlow* is an open-source indus\u00adtry-dri\u00adven deploy\u00adment tool that pro\u00advi\u00addes a fast expe\u00adri\u00adence on Intel archi\u00adtec\u00adtu\u00adre, ease of instal\u00adla\u00adti\u00adon and simp\u00adle&nbsp;use.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p><span class=\"small\"><sup>1<\/sup>Intel cal\u00adcu\u00adla\u00adted 2022 total addressa\u00adble mar\u00adket oppor\u00adtu\u00adni\u00adty deri\u00adved from indus\u00adtry ana\u00adlyst reports and inter\u00adnal estimates.<\/span><\/p>\n<p><span class=\"small\"><sup>2<\/sup>Avera\u00adge idle read laten\u00adcy is the mean time for read data to return to a reques\u00adt\u00ading pro\u00adces\u00adsor. This is an avera\u00adge; some laten\u00adci\u00ades will be lon\u00adger. Tests docu\u00adment per\u00adfor\u00admance of com\u00adpon\u00adents on a par\u00adti\u00adcu\u00adlar test, in spe\u00adci\u00adfic sys\u00adtems. Dif\u00adfe\u00adren\u00adces in hard\u00adware, soft\u00adware or con\u00adfi\u00adgu\u00adra\u00adti\u00adon will affect actu\u00adal per\u00adfor\u00admance. Con\u00adsult other sources of infor\u00adma\u00adti\u00adon to eva\u00adlua\u00adte per\u00adfor\u00admance as you con\u00adsider your purcha\u00adse. For more com\u00adple\u00adte infor\u00adma\u00adti\u00adon about per\u00adfor\u00admance and bench\u00admark results, visit www.intel.com\/benchmarks.<\/span><\/p>\n<p><span class=\"small\">For\u00adward-Loo\u00adking Statements<\/span><\/p>\n<p><span class=\"small\">State\u00adments in this news sum\u00adma\u00adry that refer to future plans and expec\u00adta\u00adti\u00adons, inclu\u00adding with respect to Intel\u2019s future pro\u00adducts and the expec\u00adted avai\u00adla\u00adbi\u00adli\u00adty and bene\u00adfits of such pro\u00adducts, are for\u00adward-loo\u00adking state\u00adments that invol\u00adve a num\u00adber of risks and uncer\u00adtain\u00adties. Words such as \u201canti\u00adci\u00adpa\u00adtes,\u201d \u201cexpects,\u201d \u201cintends,\u201d \u201cgoals,\u201d \u201cplans,\u201d \u201cbelie\u00adves,\u201d \u201cseeks,\u201d \u201cesti\u00adma\u00adtes,\u201d \u201ccon\u00adti\u00adnues,\u201d \u201cmay,\u201d \u201cwill,\u201d \u201cwould,\u201d \u201cshould,\u201d \u201ccould,\u201d and varia\u00adti\u00adons of such words and simi\u00adlar expres\u00adsi\u00adons are inten\u00added to iden\u00adti\u00adfy such for\u00adward-loo\u00adking state\u00adments. State\u00adments that refer to or are based on esti\u00adma\u00adtes, fore\u00adcasts, pro\u00adjec\u00adtions, uncer\u00adtain events or assump\u00adti\u00adons, inclu\u00adding state\u00adments rela\u00adting to total addressa\u00adble mar\u00adket (<span class=\"caps\">TAM<\/span>) or mar\u00adket oppor\u00adtu\u00adni\u00adty and anti\u00adci\u00adpa\u00adted trends in our busi\u00adnesses or the mar\u00adkets rele\u00advant to them, also iden\u00adti\u00adfy for\u00adward-loo\u00adking state\u00adments. Such state\u00adments are based on the company\u2019s cur\u00adrent expec\u00adta\u00adti\u00adons and invol\u00adve many risks and uncer\u00adtain\u00adties that could cau\u00adse actu\u00adal results to dif\u00adfer mate\u00adri\u00adal\u00adly from tho\u00adse expres\u00adsed or impli\u00aded in the\u00adse for\u00adward-loo\u00adking state\u00adments. Important fac\u00adtors that could cau\u00adse actu\u00adal results to dif\u00adfer mate\u00adri\u00adal\u00adly from the company\u2019s expec\u00adta\u00adti\u00adons are set forth in Intel\u2019s ear\u00adnings release dated Octo\u00adber 25, 2018, which is included as an exhi\u00adbit to Intel\u2019s Form 8\u2011K fur\u00adnis\u00adhed to the <span class=\"caps\">SEC<\/span> on such date. Addi\u00adtio\u00adnal infor\u00adma\u00adti\u00adon regar\u00adding the\u00adse and other fac\u00adtors that could affect Intel\u2019s results is included in Intel\u2019s <span class=\"caps\">SEC<\/span> filings, inclu\u00adding the company\u2019s most recent reports on Forms 10\u2011K and 10\u2011Q. Copies of Intel\u2019s Form 10\u2011K, 10\u2011Q and 8\u2011K reports may be obtai\u00adned by visi\u00adting our Inves\u00adtor Rela\u00adti\u00adons web\u00adsite at www.intc.com or the <span class=\"caps\">SEC<\/span>\u2019s web\u00adsite at www.sec.gov.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p><span class=\"caps\">SANTA<\/span> <span class=\"caps\">CLARA<\/span>, Calif., Dec. 12, 2018 \u2013 At Intel \u201cArchi\u00adtec\u00adtu\u00adre Day,\u201d top exe\u00adcu\u00adti\u00adves, archi\u00adtects and fel\u00adlows reve\u00ada\u00adled next-gene\u00adra\u00ad\u00adti\u00adon tech\u00adno\u00adlo\u00adgies and dis\u00adcus\u00adsed pro\u00adgress on a stra\u00adtegy to power an expan\u00adding uni\u00adver\u00adse of data-inten\u00ad\u00adsi\u00ad\u00adve workloads for PCs and other smart con\u00adsu\u00admer devices, high-speed net\u00adworks, ubi\u00adqui\u00adtous arti\u00adfi\u00adci\u00adal intel\u00adli\u00adgence (<span class=\"caps\">AI<\/span>), spe\u00adcia\u00adli\u00adzed cloud data cen\u00adters and auto\u00adno\u00admous vehic\u00adles. Intel demons\u00adtra\u00adted (\u2026) <a class=\"moretag\" href=\"https:\/\/www.planet3dnow.de\/cms\/42494-new-intel-architectures-and-technologies-target-expanded-market-opportunities\/\">Wei\u00adter\u00adle\u00adsen&nbsp;\u00bb<\/a><\/p>\n","protected":false},"author":593,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[1656,1658,1004,1657],"class_list":["post-42494","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","tag-foveros","tag-gen11","tag-intel","tag-sunny-cove","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/42494","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/593"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=42494"}],"version-history":[{"count":4,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/42494\/revisions"}],"predecessor-version":[{"id":42498,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/42494\/revisions\/42498"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=42494"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=42494"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=42494"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}