{"id":45093,"date":"2019-03-11T17:59:50","date_gmt":"2019-03-11T16:59:50","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=45093"},"modified":"2019-03-11T17:59:50","modified_gmt":"2019-03-11T16:59:50","slug":"intel-kuendigt-compute-express-link-an","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/45093-intel-kuendigt-compute-express-link-an\/","title":{"rendered":"Intel k\u00fcndigt Compute Express Link an"},"content":{"rendered":"

Nach\u00addem Nvi\u00addia heu\u00adte die \u00dcber\u00adnah\u00adme von Mel\u00adlan\u00adox ver\u00adk\u00fcn\u00addet hat<\/a> und AMD<\/span> wohl in Zukunft auf Stan\u00addards wie CCIX<\/span>, Gen\u2011Z und Open\u00adCA\u00adPI set\u00adzen wird. Stellt Intel heu\u00adte Com\u00adpu\u00adte Express Link mit dem Ziel vor einen schnel\u00adlen und effi\u00adzi\u00aden\u00adten Inter\u00adcon\u00adnect zwi\u00adschen Pro\u00adzes\u00adso\u00adren sowie Gra\u00adfik\u00adkar\u00adten, Spei\u00adcher oder spe\u00adzi\u00adel\u00adlen Beschleu\u00adni\u00adger\u00adkar\u00adten zu etablieren.<\/p>\n

<\/a><\/p>\n

Mit den Part\u00adnern Ali\u00adbaba, Cis\u00adco, Dell EMC<\/span>, Face\u00adbook, Goog\u00adle, Hew\u00adlett Packard Enter\u00adpri\u00adse, Hua\u00adwei und Micro\u00adsoft hat man ein Kon\u00adsor\u00adti\u00adum gegr\u00fcn\u00addet, das die \u201cCXL<\/span> Spe\u00adzi\u00adfi\u00adka\u00adti\u00adon 1.0\u201d allen Mit\u00adglie\u00addern zur Ver\u00adf\u00fc\u00adgung stellt. Die Arbeit dar\u00adan erfolg\u00adte bei Intel und beruht auf PCI<\/span> Express 5.0, einem Stan\u00addard des\u00adsen genaue Spe\u00adzi\u00adfi\u00adka\u00adtio\u00adnen erst im Lau\u00adfe die\u00adses Jah\u00adres fina\u00adli\u00adsiert wer\u00adden sollen.<\/p>\n

The CXL<\/span> Spe\u00adci\u00adfi\u00adca\u00adti\u00adon 1.0 enables a high-speed, effi\u00adci\u00adent inter\u00adcon\u00adnect bet\u00adween the CPU<\/span> and plat\u00adform enhance\u00adments and workload acce\u00adle\u00adra\u00adtors, such as GPUs, FPGAs and other pur\u00adpo\u00adse-built acce\u00adle\u00adra\u00adtor solu\u00adti\u00adons. The tech\u00adno\u00adlo\u00adgy is built upon the well-estab\u00adlished PCI<\/span> Express\u00ae (PCIe\u00ae) infra\u00adstruc\u00adtu\u00adre, lever\u00adaging the PCIe 5.0 phy\u00adsi\u00adcal and elec\u00adtri\u00adcal inter\u00adface to pro\u00advi\u00adde advan\u00adced pro\u00adto\u00adcol in three key areas:<\/p>\n

    \n
  1. I\/O Pro\u00adto\u00adcol<\/li>\n
  2. Memo\u00adry Pro\u00adto\u00adcol, initi\u00adal\u00adly allo\u00adwing a host to share memo\u00adry with an accelerator<\/li>\n
  3. Cohe\u00adren\u00adcy Interface<\/li>\n<\/ol>\n<\/blockquote>\n

    Fest steht aber bereits, dass sich im Ver\u00adgleich zum Vor\u00adg\u00e4n\u00adger PCI<\/span> Express 4.0, f\u00fcr den ers\u00adte Pro\u00adduk\u00adte unter ande\u00adrem mit AMDs Zen 2 f\u00fcr Mit\u00adte des Jah\u00adres erwar\u00adtet wer\u00adden, die Band\u00adbrei\u00adte erneut ver\u00addop\u00adpeln soll.<\/p>\n

    Links zum Thema:<\/strong><\/p>\n