{"id":48832,"date":"2019-07-19T02:14:53","date_gmt":"2019-07-19T00:14:53","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=48832"},"modified":"2019-07-19T12:23:43","modified_gmt":"2019-07-19T10:23:43","slug":"amd-tritt-dem-konsortium-fuer-compute-express-link-cxl-bei","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/48832-amd-tritt-dem-konsortium-fuer-compute-express-link-cxl-bei\/","title":{"rendered":"AMD<\/span> tritt dem Konsortium f\u00fcr Compute Express Link (CXL<\/span>) bei"},"content":{"rendered":"

In einem Blog\u00adein\u00adtrag<\/a> hat AMDs Chief Tech\u00adno\u00adlo\u00adgy Offi\u00adcer Mark Paper\u00admas\u00adter<\/a> den Bei\u00adtritt zum Com\u00adpu\u00adte Express Link Kon\u00adsor\u00adti\u00adum bekannt\u00adge\u00adge\u00adben. Kon\u00adkur\u00adrent Intel hat\u00adte CXL<\/span> im M\u00e4rz vor\u00adge\u00adstellt<\/a>. Ziel ist es einen schnel\u00adlen und effi\u00adzi\u00aden\u00adten Inter\u00adcon\u00adnect zwi\u00adschen Pro\u00adzes\u00adso\u00adren sowie Gra\u00adfik\u00adkar\u00adten, Spei\u00adcher oder spe\u00adzi\u00adel\u00adlen Beschleu\u00adni\u00adger\u00adkar\u00adten zu eta\u00adblie\u00adren. Bis\u00adlang war man davon aus\u00adge\u00adgan\u00adgen, dass AMD<\/span> wohl eher auf offe\u00adne Stan\u00addards wie CCIX<\/span>, Gen\u2011Z oder Open\u00adCA\u00adPI set\u00adzen wird.<\/p>\n

Nach\u00addem sich zu den neun Gr\u00fcn\u00addungs\u00admit\u00adglie\u00addern Ali\u00adbaba, Cis\u00adco, Dell EMC<\/span>, Face\u00adbook, Goog\u00adle, Hew\u00adlett Packard Enter\u00adpri\u00adse, Hua\u00adwei, Intel und Micro\u00adsoft aber mitt\u00adler\u00adwei\u00adle \u00fcber 40 wei\u00adte\u00adre Fir\u00admen<\/a> \u2014 unter ande\u00adrem ARM<\/span>, Broad\u00adcom, Giga\u00adbyte, Mel\u00adlan\u00adox (Nvi\u00addia), Super\u00admi\u00adcro und Syn\u00adop\u00adsis \u2014 gesellt haben, kann man sich dem Stan\u00addard wahr\u00adschein\u00adlich nicht verschlie\u00dfen.<\/p>\n

Die Arbeit am Stan\u00addard erfolg\u00adte bei Intel und beruht auf PCI-Express 5.0. Mitt\u00adler\u00adwei\u00adle wur\u00adde die CXL<\/span> 1.1 Spe\u00adzi\u00adfi\u00adka\u00adti\u00adon her\u00adaus\u00adge\u00adge\u00adben, wobei die Spe\u00adzi\u00adfi\u00adka\u00adtio\u00adnen nur Fir\u00admen zur Ver\u00adf\u00fc\u00adgung gestellt wer\u00adden, die dem Kon\u00adsor\u00adti\u00adum ange\u00adh\u00f6\u00adren. Des\u00adhalb erstaunt die Aus\u00adsa\u00adge von Paper\u00admas\u00adter etwas, in der er CXL<\/span> als offe\u00adnen Indus\u00adtrie\u00adstan\u00addard beschreibt und sogar auf die Rol\u00adle AMDs als lang\u00adj\u00e4h\u00adri\u00adger Unter\u00adst\u00fct\u00adzer von offe\u00adnen Stan\u00addards hinweist.<\/p>\n

Com\u00adpu\u00adte Express Link (CXL<\/span>) is an open indus\u00adtry stan\u00addard inter\u00adcon\u00adnect offe\u00adring high-band\u00adwidth, low-laten\u00adcy con\u00adnec\u00adti\u00advi\u00adty bet\u00adween host pro\u00adces\u00adsors, sys\u00adtems and devices such as acce\u00adle\u00adra\u00adtor cards, memo\u00adry buf\u00adfers, and smart I\/O devices.<\/p>\n

Sin\u00adce 2016 AMD<\/span> has play\u00aded a lea\u00adder\u00adship role in dri\u00adving three other new bus\/interconnect stan\u00addards, CCIX<\/span>, Open\u00adCA\u00adPI and Gen\u2011Z. Like CXL<\/span>, the\u00adse three efforts are dri\u00adven by the need to crea\u00adte tigh\u00adter cou\u00adpling and cohe\u00adren\u00adcy bet\u00adween pro\u00adces\u00adsors and acce\u00adle\u00adra\u00adtors, and bet\u00adter exploit new and emer\u00adging memory\/storage tech\u00adno\u00adlo\u00adgies in open, stan\u00addards-based solutions.<\/p>\n

While the\u00adse dif\u00adfe\u00adrent groups have been working to sol\u00adve simi\u00adlar pro\u00adblems, each approach has its dif\u00adfe\u00adren\u00adces. As a long-stan\u00adding sup\u00adport\u00ader of open stan\u00addards, we\u2019re exci\u00adted to join CXL<\/span> and the pos\u00adsi\u00adbi\u00adli\u00adties pre\u00adsen\u00adted as we work with other eco\u00adsys\u00adtem lea\u00adders to address chal\u00adlenges we face as an industry.<\/p>\n

Mark Paper\u00admas\u00adter, CTO<\/span> AMD<\/span> (Quel\u00adle: AMD<\/span> Busi\u00adness Blog<\/a>)<\/p><\/blockquote>\n

<\/a>
Schau\u00adbild PCI<\/span>\u2011E und CLX<\/span> auf einem Link (Quel\u00adle: CXL<\/span> Konsortium)<\/figcaption><\/figure>\n

F\u00fcr den Stan\u00addard selbst exis\u00adtiert ein White\u00adpa\u00adper<\/a>, das einen kur\u00adzen \u00dcber\u00adblick gibt. CXL<\/span> l\u00e4uft auf dem PCI-Express Lay\u00ader und unter\u00adst\u00fctzt x16, x8 und x4 nativ, sowie x2 und x1 in einem her\u00adab\u00adge\u00adsetz\u00adten Modus. CXL<\/span> 1.0 star\u00adtet mit 32 Giga\u00adtrans\u00adfer pro Sekun\u00adde und bie\u00adtet eine Band\u00adbrei\u00adte von 64 GiB\/s in jede Rich\u00adtung, au\u00dfer\u00addem unter\u00adst\u00fctzt es auch Daten\u00adra\u00adten von 16,0 GT<\/span>\/s und 8,0 GT<\/span>\/s im her\u00adab\u00adge\u00adsetz\u00adten Modus.<\/p>\n","protected":false},"excerpt":{"rendered":"

In einem Blog\u00adein\u00adtrag<\/a> hat AMDs Chief Tech\u00adno\u00adlo\u00adgy Offi\u00adcer Mark Paper\u00admas\u00adter<\/a> den Bei\u00adtritt zum Com\u00adpu\u00adte Express Link Kon\u00adsor\u00adti\u00adum bekannt\u00adge\u00adge\u00adben. Kon\u00adkur\u00adrent Intel hat\u00adte CXL<\/span> im M\u00e4rz vor\u00adge\u00adstellt<\/a>. Ziel ist es einen schnel\u00adlen und effi\u00adzi\u00aden\u00adten Inter\u00adcon\u00adnect zwi\u00adschen Pro\u00adzes\u00adso\u00adren sowie Gra\u00adfik\u00adkar\u00adten, Spei\u00adcher oder spe\u00adzi\u00adel\u00adlen Beschleu\u00adni\u00adger\u00adkar\u00adten zu eta\u00adblie\u00adren. Bis\u00adlang war man davon aus\u00adge\u00adgan\u00adgen, dass AMD<\/span> wohl eher auf offe\u00adne Stan\u00addards wie CCIX<\/span>, Gen\u2011Z oder Open\u00adCA\u00adPI set\u00adzen wird. (\u2026) Wei\u00adter\u00adle\u00adsen \u00bb<\/a><\/p>\n","protected":false},"author":593,"featured_media":45097,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[12,11],"tags":[1793,1791,1792,1004],"class_list":["post-48832","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-aktuelles","category-news","tag-ccix","tag-clx","tag-gen-z","tag-intel","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/48832","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/593"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=48832"}],"version-history":[{"count":6,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/48832\/revisions"}],"predecessor-version":[{"id":48876,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/48832\/revisions\/48876"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media\/45097"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=48832"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=48832"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=48832"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}