{"id":49051,"date":"2019-07-29T13:05:40","date_gmt":"2019-07-29T11:05:40","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=49051"},"modified":"2019-07-29T19:47:08","modified_gmt":"2019-07-29T17:47:08","slug":"dram-calculator-for-ryzen-v1-6-0","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/49051-dram-calculator-for-ryzen-v1-6-0\/","title":{"rendered":"DRAM<\/span> Calculator for Ryzen v1.6.0.1"},"content":{"rendered":"

Der \u201cDRAM<\/span> Cal\u00adcu\u00adla\u00adtor for Ryzen\u201d hilft beim \u00dcber\u00adtak\u00adten des Arbeits\u00adspei\u00adchers auf Platt\u00adfor\u00admen mit AMDs Ryzen-Pro\u00adzes\u00adso\u00adren, indem auf Basis der Daten des ein\u00adge\u00adsetz\u00adten Arbeits\u00adspei\u00adchers Vor\u00adschl\u00e4\u00adge f\u00fcr die Ein\u00adstel\u00adlun\u00adgen der Timings gemacht wer\u00adden. Die Ver\u00adsi\u00adon 1.6.0.1 bie\u00adtet nun Unter\u00adst\u00fct\u00adzung f\u00fcr Pro\u00adzes\u00adso\u00adren auf Basis von AMDs Zen 2 und f\u00fcr Main\u00adboards mit X570-Chipsatz.<\/p>\n

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Chan\u00adge\u00adlog 1.6.0.1:<\/strong><\/p>\n

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  • Added full sup\u00adport for Zen 2<\/b> and X570<\/span><\/b> motherboards.<\/li>\n
  • Added recom\u00admen\u00adda\u00adti\u00adons for VDDG<\/span><\/b> and FCLK<\/span><\/b> for Zen 2.<\/li>\n
  • Added recom\u00admen\u00adda\u00adti\u00adons for Vref (CHA<\/span> \/ CHB<\/span>)<\/b>.<\/li>\n
  • The maxi\u00admum fre\u00adquen\u00adcy for 1:1 mode is now 3800 MHz, and for 2:1 mode \u2014 4200.<\/li>\n
  • Updated pre\u00adsets for Sam\u00adsung b\u2011die, Hynix CJR<\/span> and Micron e\u2011die.<\/li>\n
  • Added back\u00adward com\u00adpa\u00adti\u00adbi\u00adli\u00adty of Zen 2 with pre\u00advious gene\u00adra\u00adti\u00adons of motherboards.<\/li>\n
  • Added PMU<\/span> Trai\u00adning<\/b> recom\u00admen\u00adda\u00adti\u00adons for all Ryzen plat\u00adforms. Bet\u00adter trai\u00adning \u2014 a more sta\u00adble system.<\/li>\n
  • Added auto\u00adsa\u00adve of the main tab set\u00adtings when clo\u00adsing the pro\u00adgram and auto\u00adma\u00adti\u00adcal\u00adly loa\u00adding them when the pro\u00adgram is started.<\/li>\n
  • Impro\u00adved tWRRD pre\u00addic\u00adtion for Dual Rank.<\/li>\n
  • Color noti\u00adfi\u00adca\u00adti\u00adon<\/b> of vol\u00adta\u00adge limits and FCLK<\/span>. Black is the norm, red is the limit.<\/li>\n
  • Timing detec\u00adtion for Zen and Zen + gene\u00adra\u00adti\u00adons. For the gene\u00adra\u00adti\u00adon Zen 2 at the moment the\u00adre is no pos\u00adsi\u00adbi\u00adli\u00adty to add a defi\u00adni\u00adti\u00adon of timings due to NDA<\/span>. Unfortunately.<\/li>\n
  • Fixed a lack of pre\u00adsets for X399<\/span>.<\/li>\n
  • Fixed a rare error in which it was impos\u00adsi\u00adble to cal\u00adcu\u00adla\u00adte the timings.<\/li>\n
  • Added a but\u00adton to access the Inter\u00adnet over\u00adclo\u00adcking sta\u00adtis\u00adtics gene\u00adra\u00adti\u00adon Zen 2<\/b>.<\/li>\n
  • For users of Intel<\/b> sys\u00adtems in the \u201cAddi\u00adtio\u00adnal Cal\u00adcu\u00adla\u00adtors\u201d sec\u00adtion, it is pos\u00adsi\u00adble to cal\u00adcu\u00adla\u00adte tRE\u00adFI<\/b> and RTL<\/span> IO<\/span>\u2011L<\/b>.<\/li>\n
  • Added 2 new laten\u00adcy tests for MEM\u00adbench<\/b>. Cus\u00adtom laten\u00adcy<\/b> is a memo\u00adry access test that the pro\u00adces\u00adsor can\u00adnot pre\u00addict (using a spe\u00adci\u00adfic off\u00adset). Ran\u00addom laten\u00adcy<\/b> \u2014 the avera\u00adge time is mea\u00adsu\u00adred for ran\u00addom memo\u00adry acces\u00adses in a buf\u00adfer of a cer\u00adtain size. Par\u00adti\u00adal\u00adly affects the result of TLB<\/span>. Both ver\u00adsi\u00adons are release can\u00addi\u00adda\u00adtes, but I do not deny that the\u00adre will be calibrations.<\/li>\n
  • Cus\u00adtom laten\u00adcy and Ran\u00addom laten\u00adcy are included in the Easy and Default packa\u00adges. Plea\u00adse note that during test\u00ading the pro\u00adgram will open \/ clo\u00adse the prompt its\u00adelf (you do not need to deal with it).<\/li>\n
  • Added infor\u00adma\u00adti\u00adon about the size of the L3<\/span> cache pro\u00adces\u00adsor. Also, the size of the test blocks for laten\u00adcy tests is con\u00adtrol\u00adled rela\u00adti\u00adve to it.<\/li>\n
  • Added but\u00adton Clear stand\u00adby<\/b>. The\u00adre is to clean the cached memo\u00adry by the ope\u00adra\u00adting sys\u00adtem. Did\u00adn\u2019t the test run? \u2014 Click Clear standby.<\/li>\n
  • Max RAM<\/span> but\u00adton bet\u00adter deter\u00admi\u00adnes the amount of free memo\u00adry available for test\u00ading. Useful for che\u00adcking memo\u00adry for errors.<\/li>\n
  • The\u00adre are excep\u00adti\u00adons for many func\u00adtions. Fault tole\u00adrance of the pro\u00adgram increased.<\/li>\n
  • Gra\u00adphic edits.<\/li>\n<\/ul>\n<\/div>\n<\/div>\n<\/blockquote>\n