{"id":49384,"date":"2019-08-06T22:25:00","date_gmt":"2019-08-06T20:25:00","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=49384"},"modified":"2019-08-06T22:25:00","modified_gmt":"2019-08-06T20:25:00","slug":"xilinx-expands-alveo-portfolio-with-industrys-first-adaptable-compute-network-and-storage-accelerator-card-built-for-any-server-any-cloud","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/49384-xilinx-expands-alveo-portfolio-with-industrys-first-adaptable-compute-network-and-storage-accelerator-card-built-for-any-server-any-cloud\/","title":{"rendered":"Xilinx Expands Alveo Portfolio with Industry\u2019s First Adaptable Compute, Network and Storage Accelerator Card Built for Any Server, Any&nbsp;Cloud"},"content":{"rendered":"<p><strong>First low-pro\u00adfi\u00adle PCIe Gen 4 card deli\u00advers dra\u00adma\u00adtic impro\u00adve\u00adments in through\u00adput, laten\u00adcy and power effi\u00adci\u00aden\u00adcy for cri\u00adti\u00adcal data cen\u00adter workloads<\/strong><\/p>\n<p><span class=\"xn-location\"><span class=\"caps\">SAN<\/span> <span class=\"caps\">JOSE<\/span>, Calif.<\/span>,&nbsp;<span class=\"xn-chron\">Aug. 6, 2019<\/span>&nbsp;\/PRNewswire\/ \u2014&nbsp;Xilinx, Inc. (<span class=\"caps\">NASDAQ<\/span>: <span class=\"caps\">XLNX<\/span>), the lea\u00adder in adap\u00adti\u00adve and intel\u00adli\u00adgent com\u00adpu\u00adting, today expan\u00added its Alveo data cen\u00adter acce\u00adle\u00adra\u00adtor card port\u00adfo\u00adlio with the launch of the Alveo<sup>\u2122<\/sup>&nbsp;<span class=\"caps\">U50<\/span>. The <span class=\"caps\">U50<\/span> card is the industry\u2019s first low pro\u00adfi\u00adle adap\u00adta\u00adble acce\u00adle\u00adra\u00adtor with PCIe Gen 4 sup\u00adport, uni\u00adque\u00adly desi\u00adgned to super\u00adchar\u00adge a broad ran\u00adge of cri\u00adti\u00adcal com\u00adpu\u00adte, net\u00adwork and sto\u00adrage workloads, all on one recon\u00adfi\u00adgura\u00adble platform.<\/p>\n<p>&nbsp;<\/p>\n<figure id=\"attachment_49385\" aria-describedby=\"caption-attachment-49385\" style=\"width: 300px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/08\/xilinx_alveou50.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"size-medium wp-image-49385\" src=\"https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/08\/xilinx_alveou50-300x165.jpg\" alt width=\"300\" height=\"165\" srcset=\"https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/08\/xilinx_alveou50-300x165.jpg 300w, https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/08\/xilinx_alveou50.jpg 400w\" sizes=\"auto, (max-width: 300px) 100vw, 300px\"><\/a><figcaption id=\"caption-attachment-49385\" class=\"wp-caption-text\">Alveo <span class=\"caps\">U50<\/span> Data Cen\u00adter Acce\u00adle\u00adra\u00adtor Card (PRNewsfoto\/Xilinx, Inc.)<\/figcaption><\/figure>\n<p>The Alveo <span class=\"caps\">U50<\/span> pro\u00advi\u00addes cus\u00adto\u00admers with a pro\u00adgramma\u00adble low pro\u00adfi\u00adle and low-power acce\u00adle\u00adra\u00adtor plat\u00adform built for sca\u00adle-out archi\u00adtec\u00adtures and domain-spe\u00adci\u00adfic acce\u00adle\u00adra\u00adti\u00adon of any ser\u00adver deploy\u00adment, on-pre\u00admi\u00adse, in the cloud and at the edge. To meet the chal\u00adlenges of emer\u00adging dyna\u00admic workloads such as cloud micro\u00adser\u00advices, Alveo <span class=\"caps\">U50<\/span> deli\u00advers bet\u00adween 10\u201320x impro\u00adve\u00adments in through\u00adput, laten\u00adcy and power effi\u00adci\u00aden\u00adcy. For acce\u00adle\u00adra\u00adted net\u00adwor\u00adking and sto\u00adrage workloads, the <span class=\"caps\">U50<\/span> card helps deve\u00adlo\u00adpers iden\u00adti\u00adfy and eli\u00admi\u00adna\u00adte laten\u00adcy and data move\u00adment bot\u00adt\u00adlen\u00adecks by moving com\u00adpu\u00adte clo\u00adser to the&nbsp;data.<\/p>\n<p>Powered by the Xilinx<sup>\u00ae<\/sup>&nbsp;UltraS\u00adca\u00adle+\u2122 archi\u00adtec\u00adtu\u00adre, the Alveo <span class=\"caps\">U50<\/span> card is the first in the Alveo port\u00adfo\u00adlio to be packa\u00adged in a half-height, half-length form fac\u00adtor and low 75-Watt power enve\u00adlo\u00adpe. The card fea\u00adtures high-band\u00adwidth memo\u00adry (<span class=\"caps\">HBM2<\/span>), 100 giga\u00adbit per second (100 Gbps) net\u00adwor\u00adking con\u00adnec\u00adti\u00advi\u00adty, and sup\u00adport for the PCIe Gen 4 and <span class=\"caps\">CCIX<\/span> inter\u00adcon\u00adnects. By fit\u00adting into stan\u00addard PCIe ser\u00adver slots and using one-third the power, the Alveo <span class=\"caps\">U50<\/span> signi\u00adfi\u00adcant\u00adly expands the scope in which adap\u00adta\u00adble acce\u00adle\u00adra\u00adti\u00adon can be deploy\u00aded to unlock dra\u00adma\u00adtic through\u00adput and laten\u00adcy impro\u00adve\u00adments for deman\u00adding com\u00adpu\u00adte, net\u00adwork and sto\u00adrage workloads. The <span class=\"caps\">8GB<\/span> of <span class=\"caps\">HBM2<\/span> deli\u00advers over 400 Gbps data trans\u00adfer speeds and the <span class=\"caps\">QSFP<\/span> ports pro\u00advi\u00adde up to 100 Gbps net\u00adwork con\u00adnec\u00adti\u00advi\u00adty. The high-speed net\u00adwor\u00adking I\/O also sup\u00adports advan\u00adced appli\u00adca\u00adti\u00adons like NVMe-oF\u2122 solu\u00adti\u00adons (<span class=\"caps\">NVM<\/span> Express over Fabrics\u2122), dis\u00adag\u00adgre\u00adga\u00adted com\u00adpu\u00adta\u00adtio\u00adnal sto\u00adrage and spe\u00adcia\u00adli\u00adzed finan\u00adcial ser\u00advices applications.&nbsp;<\/p>\n<p>From machi\u00adne lear\u00adning infe\u00adrence, video trans\u00adco\u00adding and data ana\u00adly\u00adtics to com\u00adpu\u00adta\u00adtio\u00adnal sto\u00adrage, elec\u00adtro\u00adnic tra\u00adding and finan\u00adcial risk mode\u00adling, the Alveo <span class=\"caps\">U50<\/span> brings pro\u00adgramma\u00adbi\u00adli\u00adty, fle\u00adxi\u00adbi\u00adli\u00adty, and high through\u00adput and low laten\u00adcy per\u00adfor\u00admance advan\u00adta\u00adges to any ser\u00adver deploy\u00adment. Unli\u00adke fixed archi\u00adtec\u00adtu\u00adre alter\u00adna\u00adti\u00adves, the soft\u00adware and hard\u00adware pro\u00adgramma\u00adbi\u00adli\u00adty of the Alveo <span class=\"caps\">U50<\/span> allows cus\u00adto\u00admers to meet ever-chan\u00adging demands and opti\u00admi\u00adze appli\u00adca\u00adti\u00adon per\u00adfor\u00admance as workloads and algo\u00adrith\u00adms con\u00adti\u00adnue to evolve.&nbsp;<\/p>\n<p>Alveo <span class=\"caps\">U50<\/span> acce\u00adle\u00adra\u00adted solu\u00adti\u00adons deli\u00adver signi\u00adfi\u00adcant cus\u00adto\u00admer value across a ran\u00adge of appli\u00adca\u00adti\u00adons, including:<\/p>\n<ul>\n<li>Deep lear\u00adning infe\u00adrence acce\u00adle\u00adra\u00adti\u00adon (speech trans\u00adla\u00adti\u00adon): deli\u00advers up to 25x lower laten\u00adcy, 10x hig\u00adher through\u00adput and signi\u00adfi\u00adcant\u00adly impro\u00adved power effi\u00adci\u00aden\u00adcy per node com\u00adpared to GPU-only for speech trans\u00adla\u00adti\u00adon per\u00adfor\u00admance<sup>1<\/sup>;<\/li>\n<li>Data ana\u00adly\u00adtics acce\u00adle\u00adra\u00adti\u00adon (data\u00adba\u00adse query): run\u00adning the <span class=\"caps\">TPC<\/span>\u2011H Query bench\u00admark, Alveo <span class=\"caps\">U50<\/span> deli\u00advers 4x hig\u00adher through\u00adput per hour and redu\u00adced ope\u00adra\u00adtio\u00adnal cos\u00adts by 3x com\u00adpared to in-memo\u00adry <span class=\"caps\">CPU<\/span><sup>2<\/sup>;<\/li>\n<li>Com\u00adpu\u00adta\u00adtio\u00adnal sto\u00adrage acce\u00adle\u00adra\u00adti\u00adon (com\u00adpres\u00adsi\u00adon): deli\u00advers 20x more compression\/decompression through\u00adput, fas\u00adter Hadoop and big data ana\u00adly\u00adtics, and over 30 per\u00adcent lower cost per node com\u00adpared to CPU-only nodes<sup>3<\/sup>;<\/li>\n<li>Net\u00adwork acce\u00adle\u00adra\u00adti\u00adon (elec\u00adtro\u00adnic tra\u00adding): deli\u00advers 20x lower laten\u00adcy and sub-500ns tra\u00adding time com\u00adpared to CPU-only laten\u00adcy of 10us<sup>4<\/sup>;<\/li>\n<li>Finan\u00adcial mode\u00adling (grid com\u00adpu\u00adting): run\u00adning the&nbsp;<span class=\"xn-location\">Mon\u00adte Car\u00adlo<\/span>&nbsp;simu\u00adla\u00adti\u00adon, Alveo <span class=\"caps\">U50<\/span> deli\u00advers 7x grea\u00adter power effi\u00adci\u00aden\u00adcy com\u00adpared to GPU-only per\u00adfor\u00admance<sup>5<\/sup>&nbsp;for a fas\u00adter time to insight, deter\u00admi\u00adni\u00adstic laten\u00adcy and redu\u00adced ope\u00adra\u00adtio\u00adnal&nbsp;costs.<\/li>\n<\/ul>\n<p><span class=\"dquo\">\u201c<\/span>Ever-gro\u00adwing demands on the data cen\u00adter are pushing exis\u00adting infra\u00adstruc\u00adtu\u00adre to its limit, dri\u00adving the need for adap\u00adta\u00adble solu\u00adti\u00adons that can opti\u00admi\u00adze per\u00adfor\u00admance across a broad ran\u00adge of workloads and extend the life\u00adcy\u00adcle of exis\u00adting infra\u00adstruc\u00adtu\u00adre, ulti\u00adm\u00adate\u00adly redu\u00adcing <span class=\"caps\">TCO<\/span>,\u201d said&nbsp;<span class=\"xn-person\">Salil Raje<\/span>, exe\u00adcu\u00adti\u00adve vice pre\u00adsi\u00addent and gene\u00adral mana\u00adger, Data Cen\u00adter Group, at Xilinx. \u201cThe new Alveo <span class=\"caps\">U50<\/span> brings an opti\u00admi\u00adzed form fac\u00adtor and unpre\u00adce\u00adden\u00adted per\u00adfor\u00admance and adap\u00adta\u00adbi\u00adli\u00adty to data cen\u00adter workloads, and we con\u00adti\u00adnue to build out solu\u00adti\u00adon stacks with a gro\u00adwing eco\u00adsys\u00adtem of appli\u00adca\u00adti\u00adon part\u00adners to deli\u00adver pre\u00advious\u00adly unthinkable capa\u00adbi\u00adli\u00adties to a ran\u00adge of industries.\u201d<\/p>\n<p><b>Indus\u00adtry Support<\/b><\/p>\n<p><span class=\"dquo\">\u201c<\/span>The forth\u00adco\u00adming 2<sup>nd<\/sup>&nbsp;Gen&nbsp;<span class=\"xn-person\"><span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span><\/span>&nbsp;pro\u00adces\u00adsor is ide\u00adal\u00adly sui\u00adted for data cen\u00adter-first acce\u00adle\u00adra\u00adtors like the Alveo <span class=\"caps\">U50<\/span> that com\u00adbi\u00adne com\u00adpu\u00adte, net\u00adwork and sto\u00adrage acce\u00adle\u00adra\u00adti\u00adon all on the same plat\u00adform,\u201d said&nbsp;<span class=\"xn-person\">Rag\u00adhu Nam\u00adbi\u00adar<\/span>, vice pre\u00adsi\u00addent <span class=\"amp\">&amp;<\/span> <span class=\"caps\">CTO<\/span> of appli\u00adca\u00adti\u00adon engi\u00adnee\u00adring at <span class=\"caps\">AMD<\/span>. \u201cTaking advan\u00adta\u00adge of <span class=\"caps\">AMD<\/span>\u2019s lea\u00adder\u00adship, first x86 ser\u00adver-class PCIe 4.0 <span class=\"caps\">CPU<\/span>, the Alveo <span class=\"caps\">U50<\/span> will be the industry\u2019s first adap\u00adta\u00adble acce\u00adle\u00adra\u00adtor card with PCIe 4.0 sup\u00adport. We look for\u00adward to working with Xilinx to com\u00adbi\u00adne the bene\u00adfits of <span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span> based solu\u00adti\u00adons with Alveo acce\u00adle\u00adra\u00adti\u00adon to hypers\u00adca\u00adle and enter\u00adpri\u00adse customers.\u201d<\/p>\n<p><span class=\"dquo\">\u201c<\/span><span class=\"caps\">IBM<\/span> is exci\u00adted about the expan\u00adsi\u00adon of the Xilinx Alveo port\u00adfo\u00adlio with the addi\u00adti\u00adon of the Alveo <span class=\"caps\">U50<\/span> adap\u00adta\u00adble acce\u00adle\u00adra\u00adtor card,\u201d said&nbsp;<span class=\"xn-person\">Ste\u00adve Fields<\/span>, Chief Archi\u00adtect for <span class=\"caps\">IBM<\/span> Power Sys\u00adtems. \u201cWe belie\u00adve the com\u00adbi\u00adna\u00adti\u00adon of low-pro\u00adfi\u00adle form-fac\u00adtor, <span class=\"caps\">HBM2<\/span> memo\u00adry per\u00adfor\u00admance, and PCIe Gen 4 speed to inter\u00adface with <span class=\"caps\">IBM<\/span> Power pro\u00adces\u00adsors will enable the Open\u00adPOWER eco\u00adsys\u00adtem to pro\u00advi\u00adde cut\u00adting edge adap\u00adta\u00adble acce\u00adle\u00adra\u00adti\u00adon solutions.\u201d&nbsp;<\/p>\n<p><span class=\"dquo\">\u201c<\/span>With the smal\u00adler design and advan\u00adced fea\u00adtures of the Alveo <span class=\"caps\">U50<\/span>, Xilinx is well posi\u00adtio\u00adned to expand the mar\u00adkets for acce\u00adle\u00adra\u00adti\u00adon with con\u00adfi\u00adgura\u00adble logic,\u201d said&nbsp;<span class=\"xn-person\">Karl Freund<\/span>, seni\u00ador ana\u00adlyst, <span class=\"caps\">HPC<\/span> and deep lear\u00adning, Moor Insights <span class=\"amp\">&amp;<\/span> Stra\u00adtegy. \u201cThe new Alveo <span class=\"caps\">U50<\/span> should allow them to break through the mar\u00adket noi\u00adse with demons\u00adtra\u00adted and dra\u00adma\u00adtic per\u00adfor\u00admance advan\u00adta\u00adges in high-growth use&nbsp;cases.\u201d<\/p>\n<p><span class=\"dquo\">\u201c<\/span>We are exci\u00adted to be col\u00adla\u00adbo\u00adra\u00adting with Xilinx at <span class=\"caps\">FMS<\/span>, show\u00adca\u00adsing the fle\u00adxi\u00adbi\u00adli\u00adty and per\u00adfor\u00admance of the Alveo <span class=\"caps\">U50<\/span> and our Open\u00adFlex com\u00adposable NVMe-oF plat\u00adform,\u201d said&nbsp;<span class=\"xn-person\">Scott Hamil\u00adton<\/span>, seni\u00ador direc\u00adtor of pro\u00adduct manage\u00adment, Data Cen\u00adter Sys\u00adtems busi\u00adness unit at Wes\u00adtern Digi\u00adtal. \u201cXilinx is lea\u00adding the char\u00adge in fabric-based com\u00adpu\u00adta\u00adtio\u00adnal sto\u00adrage using NVMe-oF to enable full dis\u00adag\u00adgre\u00adga\u00adti\u00adon of ser\u00adver resour\u00adces. We belie\u00adve the new Alveo <span class=\"caps\">U50<\/span> will be an important part of the eco\u00adsys\u00adtem as orga\u00adniza\u00adti\u00adons take a tru\u00adly dis\u00adag\u00adgre\u00adga\u00adted approach to <span class=\"caps\">SDS<\/span> infrastructure.\u201d<\/p>\n<p><b>Avai\u00adla\u00adbi\u00adli\u00adty:&nbsp;<br>\n<\/b>The Alveo <span class=\"caps\">U50<\/span> is sam\u00adpling now with <span class=\"caps\">OEM<\/span> sys\u00adtem qua\u00adli\u00adfi\u00adca\u00adti\u00adons in pro\u00adcess. Gene\u00adral avai\u00adla\u00adbi\u00adli\u00adty is sla\u00adted for fall&nbsp;2019.<\/p>\n<p><b>Flash Memo\u00adry Summit:&nbsp;<br>\n<\/b>Xilinx will be show\u00adca\u00adsing the&nbsp;Alveo <span class=\"caps\">U50<\/span> and other pro\u00adduct demons\u00adtra\u00adti\u00adons in booth 313 at Flash Memo\u00adry Sum\u00admit (<span class=\"caps\">FMS<\/span>) 2019, taking place&nbsp;<span class=\"xn-chron\">August 6\u20138<\/span>&nbsp;at the&nbsp;<span class=\"xn-location\">San\u00adta Cla\u00adra<\/span>&nbsp;Con\u00adven\u00adti\u00adon Cen\u00adter in&nbsp;<span class=\"xn-location\">San\u00adta Cla\u00adra<\/span>, Calif.&nbsp;<\/p>\n<p>Addi\u00adtio\u00adnal\u00adly,&nbsp;<span class=\"xn-person\">Salil Raje<\/span>, exe\u00adcu\u00adti\u00adve vice pre\u00adsi\u00addent and gene\u00adral mana\u00adger, Data Cen\u00adter Group, at Xilinx, will be giving a key\u00adnote titled, \u201cFPGAs: The Key to Acce\u00adle\u00adra\u00adting High-Speed Sto\u00adrage Sys\u00adtems\u201d on&nbsp;<span class=\"xn-chron\">August 7<\/span>&nbsp;at&nbsp;<span class=\"xn-chron\">2:40 p.m. <span class=\"caps\">PT<\/span><\/span>&nbsp;in the Mis\u00adsi\u00adon City Ballroom.<\/p>\n<p><b>About Xilinx<br>\n<\/b>Xilinx deve\u00adlo\u00adps high\u00adly fle\u00adxi\u00adble and adap\u00adti\u00adve pro\u00adces\u00adsing plat\u00adforms that enable rapid inno\u00adva\u00adti\u00adon across a varie\u00adty of tech\u00adno\u00adlo\u00adgies \u2013 from the end\u00adpoint to the edge to the cloud. Xilinx is the inven\u00adtor of the <span class=\"caps\">FPGA<\/span>, hard\u00adware pro\u00adgramma\u00adble SoCs, and the <span class=\"caps\">ACAP<\/span>, desi\u00adgned to deli\u00adver the most dyna\u00admic pro\u00adces\u00adsor tech\u00adno\u00adlo\u00adgy in the indus\u00adtry and enable the adap\u00adta\u00adble, intel\u00adli\u00adgent and con\u00adnec\u00adted world of the future. For more infor\u00adma\u00adti\u00adon, visit&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=2543635-1&amp;h=174877124&amp;u=http%3A%2F%2Fwww.xilinx.com%2F&amp;a=www.xilinx.com\" target=\"_blank\" rel=\"nofollow noopener noreferrer\">www.xilinx.com<\/a>.<\/p>\n<p>Foot\u00adno\u00adtes:<\/p>\n<ol type=\"1\">\n<li>Per\u00adfor\u00admance of Alveo <span class=\"caps\">U50<\/span>, with both Alveo <span class=\"caps\">U50<\/span> and Nvi\u00addia Tes\u00adla <span class=\"caps\">T4<\/span> run\u00adning (B=2, L=8), Tes\u00adla <span class=\"caps\">T4<\/span> (B=8, L=8) (esti\u00adma\u00adted&nbsp;data)<\/li>\n<li>Alveo <span class=\"caps\">U50<\/span>=24ms,&nbsp;<span class=\"xn-money\">150k<\/span>&nbsp;query\/hr \/ <span class=\"caps\">CPU<\/span> Query time = 210ms,&nbsp;<span class=\"xn-money\">34k<\/span>&nbsp;query\/hr. based on Intel Xeon Pla\u00adti\u00adnum 8260 Pro\u00adces\u00adsor (<span class=\"xn-money\">35.<span class=\"caps\">75M<\/span><\/span>&nbsp;Cache, 2.40 GHz) 24&nbsp;core<\/li>\n<li>Intel Sky\u00adla\u00adke-SP 6152 @2.10GHz <span class=\"caps\">CPU<\/span> (Ubun\u00adtu 16.04) <span class=\"caps\">CPU<\/span> Query time = 210ms,&nbsp;<span class=\"xn-money\">34k<\/span>&nbsp;query\/hr. Alveo <span class=\"caps\">U50<\/span>=24ms,&nbsp;<span class=\"xn-money\">150k<\/span>&nbsp;query\/hr Xilinx Alveo <span class=\"caps\">U50<\/span> SDAc\u00adcel 2018.3 (esti\u00adma\u00adte) <span class=\"caps\">GB<\/span>\/s com\u00adpres\u00adsi\u00adon per <span class=\"caps\">CPU<\/span> core = .0229. Alveo <span class=\"caps\">U50<\/span> = <span class=\"caps\">10GB<\/span>\/s (esti\u00adma\u00adte)<\/li>\n<li>Alveo <span class=\"caps\">U50<\/span> laten\u00adcy is &lt;0.5us, <span class=\"caps\">CPU<\/span> laten\u00adcy is 10us. Mea\u00adsu\u00adred from start of packet in on Tick (Mar\u00adket Data) to start of packet out on the order to Start Packet Out on the Order (esti\u00adma\u00adte)<\/li>\n<li>Intel Xeon <span class=\"caps\">E5-2697<\/span> v4 <span class=\"caps\">GCC<\/span> 5.4.0 Nvi\u00addia Tes\u00adla <span class=\"caps\">V100<\/span> <span class=\"caps\">16GB<\/span> PCIe <span class=\"caps\">CUDA<\/span> 10.1 \/ <span class=\"caps\">GCC<\/span> 5.4.0 Intel Sky\u00adla\u00adke-SP 6152 @2.10GHz <span class=\"caps\">CPU<\/span> (Ubun\u00adtu 16.04) <span class=\"caps\">CPU<\/span> Query time = 210ms,&nbsp;<span class=\"xn-money\">34k<\/span>&nbsp;query\/hr. Alveo <span class=\"caps\">U50<\/span>=24ms,&nbsp;<span class=\"xn-money\">150k<\/span>&nbsp;query\/hr Xilinx Alveo <span class=\"caps\">U50<\/span> SDAc\u00adcel 2018.3 (esti\u00adma\u00adted&nbsp;data).<\/li>\n<\/ol>\n<p><i>\u00a9 Copy\u00adright 2019 Xilinx, Inc. Xilinx, the Xilinx logo, and other desi\u00adgna\u00adted brands included her\u00adein are trade\u00admarks of Xilinx in the United Sta\u00adtes and other count\u00adries.&nbsp;NVMe-oF and <span class=\"caps\">NVM<\/span> Express over Fabrics are trade\u00admarks of <span class=\"caps\">NVM<\/span> Express, Inc. <span class=\"caps\">PCI<\/span>, PCIe and <span class=\"caps\">PCI<\/span> Express are trade\u00admarks of <span class=\"caps\">PCI-SIG<\/span> and used under licen\u00adse. &nbsp;All other trade\u00admarks are the pro\u00adper\u00adty of their respec\u00adti\u00adve owners.<\/i><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>First low-pro\u00ad\u00adfi\u00ad\u00adle PCIe Gen 4 card deli\u00advers dra\u00adma\u00adtic impro\u00adve\u00adments in through\u00adput, laten\u00adcy and power effi\u00adci\u00aden\u00adcy for cri\u00adti\u00adcal data cen\u00adter workloads <span class=\"caps\">SAN<\/span> <span class=\"caps\">JOSE<\/span>, Calif.,&nbsp;Aug. 6, 2019&nbsp;\/PRNewswire\/ \u2014&nbsp;Xilinx, Inc. (<span class=\"caps\">NASDAQ<\/span>: <span class=\"caps\">XLNX<\/span>), the lea\u00adder in adap\u00adti\u00adve and intel\u00adli\u00adgent com\u00adpu\u00adting, today expan\u00added its Alveo data cen\u00adter acce\u00adle\u00adra\u00adtor card port\u00adfo\u00adlio with the launch of the Alveo\u2122&nbsp;<span class=\"caps\">U50<\/span>. The <span class=\"caps\">U50<\/span> card is (\u2026) <a class=\"moretag\" href=\"https:\/\/www.planet3dnow.de\/cms\/49384-xilinx-expands-alveo-portfolio-with-industrys-first-adaptable-compute-network-and-storage-accelerator-card-built-for-any-server-any-cloud\/\">Wei\u00adter\u00adle\u00adsen&nbsp;\u00bb<\/a><\/p>\n","protected":false},"author":593,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[1584,1624,1583],"class_list":["post-49384","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","tag-alveo","tag-pci-express-4-0","tag-xilinx","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/49384","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/593"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=49384"}],"version-history":[{"count":1,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/49384\/revisions"}],"predecessor-version":[{"id":49386,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/49384\/revisions\/49386"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=49384"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=49384"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=49384"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}