{"id":51010,"date":"2019-09-26T21:03:53","date_gmt":"2019-09-26T19:03:53","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=51010"},"modified":"2019-09-26T21:03:53","modified_gmt":"2019-09-26T19:03:53","slug":"arm-and-tsmc-demonstrate-industrys-first-7nm-arm-based-cowos-chiplets-for-high-performance-computing","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/51010-arm-and-tsmc-demonstrate-industrys-first-7nm-arm-based-cowos-chiplets-for-high-performance-computing\/","title":{"rendered":"Arm and <span class=\"caps\">TSMC<\/span> Demonstrate Industry\u2019s First 7nm Arm-based CoWoS\u00ae Chiplets for High-Performance Computing"},"content":{"rendered":"<p><b>Hsin\u00adchu, Tai\u00adwan R.O.C., Sep\u00adtem\u00adber 26, 2019 \u2014&nbsp;<\/b>Arm and <span class=\"caps\">TSMC<\/span>, the High-Per\u00adfor\u00admance Com\u00adpu\u00adting (<span class=\"caps\">HPC<\/span>) indus\u00adtry lea\u00adders, today announ\u00adced an indus\u00adtry-first 7nm sili\u00adcon-pro\u00adven chip\u00adlet sys\u00adtem based on mul\u00adti\u00adple Arm\u00ae cores and lever\u00adaging <span class=\"caps\">TSMC<\/span>\u2019s Chip-on-Wafer-on-Sub\u00adstra\u00adte (CoWoS\u00ae) advan\u00adced pack\u00ada\u00adging solu\u00adti\u00adon. This sin\u00adgle pro\u00adof-of-con\u00adcept chip\u00adlet sys\u00adtem suc\u00adcessful\u00adly demons\u00adtra\u00adtes the key tech\u00adno\u00adlo\u00adgies for buil\u00adding an <span class=\"caps\">HPC<\/span> Sys\u00adtem-On-Chip (SoC) with Arm-based cores ope\u00adra\u00adting at 4GHz in a 7nm Fin\u00adFET pro\u00adcess. The chip\u00adlet sys\u00adtem also demons\u00adtra\u00adtes for SoC desi\u00adgners an on-die, bi-direc\u00adtion\u00adal inter\u00adcon\u00adnect mesh bus ope\u00adra\u00adting at 4GHz, and a chip\u00adlet design metho\u00addo\u00adlo\u00adgy con\u00adnec\u00adted by an 8Gb\/s inter-chip\u00adlet inter\u00adcon\u00adnect over a <span class=\"caps\">TSMC<\/span> CoWoS interposer.<\/p>\n<p>Rather than the tra\u00addi\u00adtio\u00adnal SoC approach of com\u00adbi\u00adning every sys\u00adtem com\u00adpo\u00adnent onto a sin\u00adgle die, chip\u00adlet designs are opti\u00admi\u00adzed for modern <span class=\"caps\">HPC<\/span> pro\u00adces\u00adsors which par\u00adti\u00adti\u00adon lar\u00adge mul\u00adti-core designs into smal\u00adler chip\u00adsets. This effi\u00adci\u00adent approach enables func\u00adtions to be split into smal\u00adler, sepa\u00adra\u00adte dies which pro\u00advi\u00adde for the fle\u00adxi\u00adbi\u00adli\u00adty of pro\u00addu\u00adcing each chip\u00adlet on dif\u00adfe\u00adrent pro\u00adcess tech\u00adno\u00adlo\u00adgies, as well as deli\u00adve\u00adring bet\u00adter yields and over\u00adall cost effec\u00adti\u00adve\u00adness. And to ensu\u00adre the hig\u00adhest levels of per\u00adfor\u00admance, chip\u00adlets must com\u00admu\u00adni\u00adca\u00adte with each other through den\u00adse, high-speed, high-band\u00adwidth con\u00adnec\u00adtions. To address this chall\u00adenge, this chip\u00adlet sys\u00adtem fea\u00adtures a uni\u00adque Low-vol\u00adta\u00adge-IN-Packa\u00adge-INter\u00adCON\u00adnect (<span class=\"caps\">LIPINCON<\/span><sup><span class=\"caps\">TM<\/span><\/sup>) deve\u00adlo\u00adped by <span class=\"caps\">TSMC<\/span> which has rea\u00adched data rates of 8Gb\/s per pin with excel\u00adlent power effi\u00adci\u00aden\u00adcy results.<\/p>\n<p><b>Chip\u00adlet Sys\u00adtem Details<\/b><br>\nThe chip\u00adlet sys\u00adtem is com\u00adpri\u00adsed of a dual-chip\u00adlet CoWoS imple\u00admen\u00adted in 7nm, with each chip\u00adlet con\u00adtai\u00adning four Arm Cortex\u00ae-A72 pro\u00adces\u00adsors and an on-die inter\u00adcon\u00adnect mesh bus. The die-to-die inter-chip\u00adlet con\u00adnec\u00adtion fea\u00adtures sca\u00adlable 0.56pJ\/bit (pico-Joules per bit) power effi\u00adci\u00aden\u00adcy, 1.6Tb\/s\/mm2 (tera\u00adbits per second per squa\u00adre mil\u00adli\u00adme\u00adter) band\u00adwidth den\u00adsi\u00adty, and 0.<span class=\"caps\">3V<\/span> <span class=\"caps\">LIPINCON<\/span> low-vol\u00adta\u00adge inter\u00adface achie\u00adving <span class=\"caps\">8GT<\/span>\/s (Giga Tran\u00adsac\u00adtions per second) and <span class=\"caps\">320GB<\/span>\/s band\u00adwidth. The chip\u00adlet sys\u00adtem was taped out in Decem\u00adber 2018, and pro\u00addu\u00adced in April&nbsp;2019.<\/p>\n<p><span class=\"dquo\">\u201c<\/span>This latest pro\u00adof-of-con\u00adcept with our long\u00adtime part\u00adner <span class=\"caps\">TSMC<\/span> is an excel\u00adlent foun\u00adda\u00adti\u00adon for future pro\u00adduc\u00adtion-rea\u00addy infra\u00adstruc\u00adtu\u00adre SoC solu\u00adti\u00adons which will inte\u00adgra\u00adte <span class=\"caps\">TSMC<\/span>\u2019s inno\u00adva\u00adti\u00adve advan\u00adced pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgy with the unmat\u00adched fle\u00adxi\u00adbi\u00adli\u00adty and sca\u00adla\u00adbi\u00adli\u00adty of the Arm archi\u00adtec\u00adtu\u00adre,\u201d said Drew Hen\u00adry, Seni\u00ador Vice Pre\u00adsi\u00addent and Gene\u00adral Mana\u00adger of Arm\u2019s Infra\u00adstruc\u00adtu\u00adre Line of Business.<\/p>\n<p><span class=\"dquo\">\u201c<\/span>This demons\u00adtra\u00adti\u00adon chip is an excel\u00adlent show\u00adca\u00adse of the sys\u00adtem inte\u00adgra\u00adti\u00adon capa\u00adbi\u00adli\u00adties we offer to our cus\u00adto\u00admers,\u201d said Dr. Cliff Hou, Vice Pre\u00adsi\u00addent of Tech\u00adno\u00adlo\u00adgy Deve\u00adlo\u00adp\u00adment for <span class=\"caps\">TSMC<\/span>. \u201c<span class=\"caps\">TSMC<\/span>\u2019s CoWoS advan\u00adced pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgy and <span class=\"caps\">LIPINCON<\/span> inter-chip\u00adlet inter\u00adface enable cus\u00adto\u00admers to par\u00adti\u00adti\u00adon lar\u00adge mul\u00adti-core designs into smal\u00adler chip\u00adlets that deli\u00adver bet\u00adter yield and bet\u00adter eco\u00adno\u00admics. This Arm and <span class=\"caps\">TSMC<\/span> col\u00adla\u00adbo\u00adra\u00adti\u00adon fur\u00adther unleas\u00adhes our cus\u00adto\u00admers\u2019 inno\u00adva\u00adtions in high-per\u00adfor\u00admance SoC design for cloud-to-edge infra\u00adstruc\u00adtu\u00adre applications.\u201d<\/p>\n<figure id=\"attachment_51011\" aria-describedby=\"caption-attachment-51011\" style=\"width: 469px\" class=\"wp-caption aligncenter\"><a href=\"https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/09\/CoWoS-Chiplet-Photo_6866_ckr2.png\"><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-51011\" src=\"https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/09\/CoWoS-Chiplet-Photo_6866_ckr2.png\" alt width=\"469\" height=\"342\" srcset=\"https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/09\/CoWoS-Chiplet-Photo_6866_ckr2.png 469w, https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/09\/CoWoS-Chiplet-Photo_6866_ckr2-300x219.png 300w\" sizes=\"auto, (max-width: 469px) 100vw, 469px\"><\/a><figcaption id=\"caption-attachment-51011\" class=\"wp-caption-text\">Fig. 1: Dual Chip\u00adlet Floorplan<\/figcaption><\/figure>\n","protected":false},"excerpt":{"rendered":"<p>Hsin\u00adchu, Tai\u00adwan R.O.C., Sep\u00adtem\u00adber 26, 2019 \u2014&nbsp;Arm and <span class=\"caps\">TSMC<\/span>, the High-Per\u00ad\u00adfor\u00ad\u00admance Com\u00adpu\u00adting (<span class=\"caps\">HPC<\/span>) indus\u00adtry lea\u00adders, today announ\u00adced an indus\u00ad\u00adtry-first 7nm sili\u00ad\u00adcon-pro\u00ad\u00adven chip\u00adlet sys\u00adtem based on mul\u00adti\u00adple Arm\u00ae cores and lever\u00adaging <span class=\"caps\">TSMC<\/span>\u2019s Chip-on-Wafer-on-Sub\u00ad\u00ads\u00adtra\u00ad\u00adte (CoWoS\u00ae) advan\u00adced pack\u00ada\u00adging solu\u00adti\u00adon. This sin\u00adgle pro\u00adof-of-con\u00adcept chip\u00adlet sys\u00adtem suc\u00adcessful\u00adly demons\u00adtra\u00adtes the key tech\u00adno\u00adlo\u00adgies for buil\u00adding an <span class=\"caps\">HPC<\/span> Sys\u00ad\u00adtem-On-Chip (SoC) with Arm-based cores (\u2026) <a class=\"moretag\" href=\"https:\/\/www.planet3dnow.de\/cms\/51010-arm-and-tsmc-demonstrate-industrys-first-7nm-arm-based-cowos-chiplets-for-high-performance-computing\/\">Wei\u00adter\u00adle\u00adsen&nbsp;\u00bb<\/a><\/p>\n","protected":false},"author":593,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[1010,2064,540,1037],"class_list":["post-51010","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","tag-arm","tag-cowos","tag-hpc","tag-tsmc","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/51010","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/593"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=51010"}],"version-history":[{"count":1,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/51010\/revisions"}],"predecessor-version":[{"id":51012,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/51010\/revisions\/51012"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=51010"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=51010"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=51010"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}