{"id":52426,"date":"2019-11-14T09:06:35","date_gmt":"2019-11-14T08:06:35","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=52426"},"modified":"2019-11-14T09:06:35","modified_gmt":"2019-11-14T08:06:35","slug":"rambus-announces-comprehensive-pci-express-5-0-interface-solution","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/52426-rambus-announces-comprehensive-pci-express-5-0-interface-solution\/","title":{"rendered":"Rambus Announces Comprehensive <span class=\"caps\">PCI<\/span> Express 5.0 Interface Solution"},"content":{"rendered":"<p><strong>High\u00adlights:&nbsp;<\/strong><\/p>\n<ul>\n<li><em>Inte\u00adgra\u00adted and opti\u00admi\u00adzed <span class=\"caps\">PHY<\/span> and digi\u00adtal con\u00adtrol\u00adler solu\u00adti\u00adon enables high-band\u00adwidth and low-laten\u00adcy con\u00adnec\u00adti\u00advi\u00adty for next-gene\u00adra\u00adti\u00adon appli\u00adca\u00adti\u00adons in arti\u00adfi\u00adci\u00adal intel\u00adli\u00adgence (<span class=\"caps\">AI<\/span>), data cen\u00adter, high-per\u00adfor\u00admance com\u00adpu\u00adting (<span class=\"caps\">HPC<\/span>), enter\u00adpri\u00adse and cloud sto\u00adrage, and 400GbE networking<\/em><\/li>\n<li><em><span class=\"caps\">PHY<\/span> sup\u00adports both PCIe as well Com\u00adpu\u00adte Express Link (<span class=\"caps\">CXL<\/span>) con\u00adnec\u00adti\u00advi\u00adty bet\u00adween host pro\u00adces\u00adsor and workload acce\u00adle\u00adra\u00adtors for hete\u00adro\u00adge\u00adnous computing<\/em><\/li>\n<li><em>Deli\u00advers supe\u00adri\u00ador power, per\u00adfor\u00admance and area on advan\u00adced 7nm Fin\u00adFET pro\u00adcess&nbsp;node<\/em><\/li>\n<\/ul>\n<p style=\"text-align: center;\"><a href=\"https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/11\/PCIe-5.0-interface-architecture.png\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter  wp-image-52427\" src=\"https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/11\/PCIe-5.0-interface-architecture.png\" alt width=\"868\" height=\"347\" srcset=\"https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/11\/PCIe-5.0-interface-architecture.png 1000w, https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/11\/PCIe-5.0-interface-architecture-300x120.png 300w, https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/11\/PCIe-5.0-interface-architecture-768x307.png 768w, https:\/\/www.planet3dnow.de\/cms\/wp-content\/uploads\/2019\/11\/PCIe-5.0-interface-architecture-624x250.png 624w\" sizes=\"auto, (max-width: 868px) 100vw, 868px\"><\/a><\/p>\n<p><strong><span class=\"caps\">SUNNYVALE<\/span>, Calif. \u2013&nbsp;Nov. 12, 2019 \u2013<\/strong>&nbsp;<a href=\"http:\/\/www.rambus.com\/\">Ram\u00adbus Inc.<\/a>&nbsp;(<span class=\"caps\">NASDAQ<\/span>:&nbsp;<a href=\"https:\/\/finance.yahoo.com\/quote\/rmbs?ltr=1\"><span class=\"caps\">RMBS<\/span><\/a>), a pre\u00admier sili\u00adcon <span class=\"caps\">IP<\/span> and chip pro\u00advi\u00adder making data fas\u00adter and safer, today announ\u00adced it now offers a com\u00adpre\u00adhen\u00adsi\u00adve and opti\u00admi\u00adzed inter\u00adface solu\u00adti\u00adon desi\u00adgned for&nbsp;<a href=\"https:\/\/www.rambus.com\/interface-ip\/serdes\/pcie5-phy\/\"><span class=\"caps\">PCI<\/span> Express (PCIe) 5.0<\/a>, with back\u00adward com\u00adpa\u00adti\u00adbi\u00adli\u00adty to PCIe 4.0, 3.0 and 2.0. The Ram\u00adbus PCIe 5.0 inter\u00adface solu\u00adti\u00adon includes both <span class=\"caps\">PHY<\/span> and&nbsp;<a href=\"https:\/\/www.rambus.com\/interface-ip\/serdes\/pcie5-controller\/\">digi\u00adtal con\u00adtrol\u00adler<\/a>&nbsp;for easy SoC inte\u00adgra\u00adti\u00adon and fas\u00adter time to mar\u00adket. With the <span class=\"caps\">PHY<\/span> desi\u00adgned for an advan\u00adced 7nm pro\u00adcess node, the inte\u00adgra\u00adted solu\u00adti\u00adon offers best-in-class power, per\u00adfor\u00admance and area thanks to the indus\u00adtry-pro\u00adven engi\u00adnee\u00adring and signal inte\u00adgri\u00adty exper\u00adti\u00adse of Rambus.<\/p>\n<p><span class=\"dquo\">\u201c<\/span>Our high-speed Ser\u00adDes and memo\u00adry inter\u00adface solu\u00adti\u00adons make pos\u00adsi\u00adble ama\u00adzing advance\u00adments in per\u00adfor\u00admance-inten\u00adsi\u00adve appli\u00adca\u00adti\u00adons in <span class=\"caps\">AI<\/span>, data cen\u00adter, <span class=\"caps\">HPC<\/span>, sto\u00adrage and net\u00adwor\u00adking,\u201d said Hemant Dhul\u00adla, vice pre\u00adsi\u00addent and gene\u00adral mana\u00adger of <span class=\"caps\">IP<\/span> cores at Ram\u00adbus.&nbsp;\u201cNow we\u2019ve added PCIe 5 to our indus\u00adtry-lea\u00adding port\u00adfo\u00adlio of high-speed inter\u00adface solu\u00adti\u00adons giving chip makers ano\u00adther tool to unleash the power of their designs.\u201d<\/p>\n<p>In addi\u00adti\u00adon to the sta\u00adte-of-the-art <span class=\"caps\">PHY<\/span>, the Ram\u00adbus PCIe 5.0 solu\u00adti\u00adon includes a high-per\u00adfor\u00admance, digi\u00adtal con\u00adtrol\u00adler core from recent\u00adly acqui\u00adred Nor\u00adthwest Logic. The Ram\u00adbus <span class=\"caps\">PHY<\/span> and con\u00adtrol\u00adler are offe\u00adred as a ful\u00adly vali\u00adda\u00adted and inte\u00adgra\u00adted solu\u00adti\u00adon, or they can be licen\u00adsed sepa\u00adra\u00adte\u00adly and used with third-par\u00adty solu\u00adti\u00adons. The enti\u00adre solu\u00adti\u00adon is backed by Ram\u00adbus design, inte\u00adgra\u00adti\u00adon and sup\u00adport ser\u00advices for first-time cus\u00adto\u00admer success.<\/p>\n<p><strong>Bene\u00adfits of Ram\u00adbus PCIe 5.0 Solution<\/strong><\/p>\n<ul>\n<li>Inte\u00adgra\u00adted and co-vali\u00adda\u00adted <span class=\"caps\">PHY<\/span> and digi\u00adtal con\u00adtrol\u00adler for com\u00adple\u00adte inter\u00adface solution<\/li>\n<li>Built with Ram\u00adbus\u2019 indus\u00adtry-pro\u00adven design metho\u00addo\u00adlo\u00adgy for long-reach PCIe interfaces<\/li>\n<li>32 <span class=\"caps\">GT<\/span>\/s band\u00adwidth per lane with 128 <span class=\"caps\">GB<\/span>\/s band\u00adwidth in x16 configuration<\/li>\n<li>Back\u00adward com\u00adpa\u00adti\u00adble to PCIe 4.0, 3.0 and 2.0<\/li>\n<li><span class=\"caps\">PHY<\/span> Sup\u00adports Com\u00adpu\u00adte Express Link interconnect<\/li>\n<li>Advan\u00adced mul\u00adti-tap trans\u00adcei\u00adver and recei\u00adver equa\u00adliza\u00adti\u00adon com\u00adpen\u00adsa\u00adte for more than 36dB of inser\u00adti\u00adon&nbsp;loss<\/li>\n<li>Best-in-class power, per\u00adfor\u00admance and&nbsp;area<\/li>\n<li>Sup\u00adports per\u00adfor\u00admance-inten\u00adsi\u00adve appli\u00adca\u00adti\u00adons inclu\u00adding <span class=\"caps\">AI<\/span>, data cen\u00adter, <span class=\"caps\">HPC<\/span>, sto\u00adrage and 400GbE networking<\/li>\n<\/ul>\n<p><strong>Avai\u00adla\u00adbi\u00adli\u00adty and Addi\u00adtio\u00adnal Information<br>\n<\/strong>The new Ram\u00adbus PCIe 5.0 solu\u00adti\u00adon is available world\u00adwi\u00adde in an advan\u00adced 7nm Fin\u00adFET process.<\/p>\n<p>For more infor\u00adma\u00adti\u00adon on our com\u00adple\u00adte fami\u00adly of Ser\u00adDes solu\u00adti\u00adons, plea\u00adse visit&nbsp;<a href=\"https:\/\/www.rambus.com\/interface-ip\/serdes\/\">rambus.com\/serdes<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>High\u00adlights:&nbsp; Inte\u00adgra\u00adted and opti\u00admi\u00adzed <span class=\"caps\">PHY<\/span> and digi\u00adtal con\u00adtrol\u00adler solu\u00adti\u00adon enables high-ban\u00add\u00ad\u00adwidth and low-laten\u00ad\u00adcy con\u00adnec\u00adti\u00advi\u00adty for next-gene\u00adra\u00ad\u00adti\u00adon appli\u00adca\u00adti\u00adons in arti\u00adfi\u00adci\u00adal intel\u00adli\u00adgence (<span class=\"caps\">AI<\/span>), data cen\u00adter, high-per\u00ad\u00adfor\u00ad\u00admance com\u00adpu\u00adting (<span class=\"caps\">HPC<\/span>), enter\u00adpri\u00adse and cloud sto\u00adrage, and 400GbE net\u00adwor\u00adking <span class=\"caps\">PHY<\/span> sup\u00adports both PCIe as well Com\u00adpu\u00adte Express Link (<span class=\"caps\">CXL<\/span>) con\u00adnec\u00adti\u00advi\u00adty bet\u00adween host pro\u00adces\u00adsor and workload acce\u00adle\u00adra\u00adtors for hete\u00adro\u00adge\u00adnous com\u00adpu\u00adting Deli\u00advers supe\u00adri\u00ador (\u2026) <a class=\"moretag\" href=\"https:\/\/www.planet3dnow.de\/cms\/52426-rambus-announces-comprehensive-pci-express-5-0-interface-solution\/\">Wei\u00adter\u00adle\u00adsen&nbsp;\u00bb<\/a><\/p>\n","protected":false},"author":593,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[1790,2111,1146],"class_list":["post-52426","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","tag-cxl","tag-pcie-5-0","tag-rambus","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/52426","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/593"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=52426"}],"version-history":[{"count":2,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/52426\/revisions"}],"predecessor-version":[{"id":52429,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/52426\/revisions\/52429"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=52426"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=52426"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=52426"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}