{"id":54362,"date":"2020-01-31T09:29:16","date_gmt":"2020-01-31T08:29:16","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=54362"},"modified":"2020-01-31T11:09:45","modified_gmt":"2020-01-31T10:09:45","slug":"dram-calculator-for-ryzen-v1-7-0","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/54362-dram-calculator-for-ryzen-v1-7-0\/","title":{"rendered":"DRAM<\/span> Calculator for Ryzen v1.7.0"},"content":{"rendered":"

Der \u201cDRAM<\/span> Cal\u00adcu\u00adla\u00adtor for Ryzen\u201d hilft beim \u00dcber\u00adtak\u00adten des Arbeits\u00adspei\u00adchers auf Platt\u00adfor\u00admen mit AMDs Ryzen-Pro\u00adzes\u00adso\u00adren, indem auf Basis der Daten des ein\u00adge\u00adsetz\u00adten Arbeits\u00adspei\u00adchers Vor\u00adschl\u00e4\u00adge f\u00fcr die Ein\u00adstel\u00adlun\u00adgen der Timings gemacht wer\u00adden. Seit der Ver\u00adsi\u00adon 1.6.0.1 wer\u00adden Pro\u00adzes\u00adso\u00adren auf Basis von AMDs Zen 2 und Main\u00adboards mit X570-Chip\u00adsatz unterst\u00fctzt.<\/p>\n

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Chan\u00adge\u00adlog:<\/strong><\/p>\n

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  • Added the func\u00adtion\u00ada\u00adli\u00adty to read cur\u00adrent memo\u00adry timings for Zen 2 (AM4<\/span>).<\/li>\n
  • Added a memo\u00adry band\u00adwidth test (Read and Write).<\/li>\n
  • Added an Inter-Core Laten\u00adcy test (AM4<\/span>).<\/li>\n
  • Impro\u00adved the accu\u00adra\u00adcy of Ran\u00addom and Cus\u00adtom laten\u00adcy test.<\/li>\n
  • Some chan\u00adges in the sug\u00adgested CAD_BUS<\/span> set\u00adtings. This could offer a signi\u00adfi\u00adcant impro\u00adve\u00adment in sta\u00adbi\u00adli\u00adty for con\u00adfi\u00adgu\u00adra\u00adti\u00adons with 2 or more RAM<\/span> modules.<\/li>\n
  • VDDG<\/span> set\u00adting is now divi\u00added into 2 inde\u00adpen\u00addent set\u00adtings : VDDG<\/span> IOD<\/span> and VDDG<\/span> CCD<\/span> vol\u00adta\u00adge (as in AGESA<\/span> 1004B<\/span> bioses).<\/li>\n
  • \u201c<\/span>Compa\u00adre timings\u201d now works for Zen 2 (AM4<\/span>).<\/li>\n
  • Added sup\u00adport for 3000 series Thre\u00adad\u00adrip\u00adper cpu\u2019s (Cast\u00adle Peak).<\/li>\n
  • Minor user expe\u00adri\u00adence GUI<\/span> changes.<\/li>\n
  • Added sup\u00adport for Hynix DJR<\/span> (a new CJR<\/span> revi\u00adsi\u00adon that has back\u00adward com\u00adpa\u00adti\u00adbi\u00adli\u00adty with clas\u00adsic CJR<\/span>).<\/li>\n
  • Minor bug\u00adfi\u00adxes<\/li>\n<\/ul>\n<\/blockquote>\n