{"id":55319,"date":"2020-02-26T23:25:02","date_gmt":"2020-02-26T22:25:02","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=55319"},"modified":"2020-02-26T23:25:02","modified_gmt":"2020-02-26T22:25:02","slug":"synopsys-delivers-silicon-proven-hbm2e-phy-ip-operating-at-3-2-gbps","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/55319-synopsys-delivers-silicon-proven-hbm2e-phy-ip-operating-at-3-2-gbps\/","title":{"rendered":"Synopsys Delivers Silicon-Proven <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">PHY<\/span> <span class=\"caps\">IP<\/span> Operating at 3.2&nbsp;Gbps"},"content":{"rendered":"<div class=\"wd_subtitle wd_language_left\">Design\u00adWa\u00adre <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">PHY<\/span> <span class=\"caps\">IP<\/span> in <span class=\"caps\">TSMC<\/span>\u2019s <span class=\"caps\">N7<\/span> Pro\u00adcess Deli\u00advers High Through\u00adput for Advan\u00adced Gra\u00adphics, High-Per\u00adfor\u00admance Com\u00adpu\u00adting and Net\u00adwor\u00adking&nbsp;SoCs<\/div>\n<div>&nbsp;<\/div>\n<div>\n<p><span class=\"xn-location\"><span class=\"caps\">MOUNTAIN<\/span> <span class=\"caps\">VIEW<\/span>, Calif.<\/span>,&nbsp;<span class=\"xn-chron\">Feb. 25, 2020<\/span>&nbsp;\/<a href=\"http:\/\/www.prnewswire.com\/\" target=\"_blank\" rel=\"noopener noreferrer\">PRNews\u00adwire<\/a>\/ \u2013<\/p>\n<p><b>High\u00adlights:<\/b><\/p>\n<ul type=\"disc\">\n<li>Syn\u00adop\u00adsys\u2019 Design\u00adWa\u00adre <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">IP<\/span> in <span class=\"caps\">TSMC<\/span>\u2019s <span class=\"caps\">N7<\/span> pro\u00adcess pro\u00advi\u00addes up to 409&nbsp;<span id=\"spanHghlt0a70\">GBps<\/span>&nbsp;aggre\u00adga\u00adte memo\u00adry band\u00adwidth with low-power con\u00adsump\u00adti\u00adon and latency<\/li>\n<li>The <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">PHY<\/span> has been veri\u00adfied using <span class=\"caps\">TSMC<\/span>\u2019s CoWoS\u00ae tech\u00adno\u00adlo\u00adgy inte\u00adgra\u00adting the test chip with the <span class=\"caps\">IP<\/span> and <span class=\"caps\">HBM2E<\/span> SDRAMs using 2.<span class=\"caps\">5D<\/span> packaging<\/li>\n<li>Syn\u00adop\u00adsys\u2019 sili\u00adcon-pro\u00adven <span class=\"caps\">HBM2<\/span>\/<span class=\"caps\">2E<\/span> <span class=\"caps\">IP<\/span> solu\u00adti\u00adon with har\u00addening exper\u00adti\u00adse enables desi\u00adgners to meet uni\u00adque, high-per\u00adfor\u00admance appli\u00adca\u00adti\u00adon requirements<\/li>\n<\/ul>\n<p><a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=2729407-1&amp;h=1585185583&amp;u=https%3A%2F%2Fwww.synopsys.com%2F&amp;a=Synopsys%2C+Inc.\" target=\"_blank\" rel=\"nofollow noopener noreferrer\">Syn\u00adop\u00adsys, Inc.<\/a>&nbsp;(Nasdaq:&nbsp;<span class=\"caps\">SNPS<\/span>) today announ\u00adced it has deli\u00adver\u00aded sili\u00adcon-pro\u00adven <span class=\"caps\">HBM2E<\/span>&nbsp;<span class=\"xn-person\"><span class=\"caps\">PHY<\/span> <span class=\"caps\">IP<\/span><\/span>&nbsp;ope\u00adra\u00adting at 3.2 giga\u00adbits per second (Gbps), addres\u00adsing high through\u00adput requi\u00adre\u00adments of advan\u00adced gra\u00adphics, high-per\u00adfor\u00admance com\u00adpu\u00adting and net\u00adwor\u00adking SoCs. Veri\u00adfied on <span class=\"caps\">TSMC<\/span>\u2019s Chip-on-Wafer-on-Sub\u00adstra\u00adte (CoWoS\u00ae) advan\u00adced pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgy, Syn\u00adop\u00adsys\u2019&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=2729407-1&amp;h=978366008&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fdesignware-ip%2Finterface-ip%2Fhbm2.html&amp;a=DesignWare%C2%AE+HBM2E+PHY+IP\" target=\"_blank\" rel=\"nofollow noopener noreferrer\">Design\u00adWa\u00adre<sup>\u00ae<\/sup>&nbsp;<span class=\"caps\">HBM2E<\/span>&nbsp;<span class=\"xn-person\"><span class=\"caps\">PHY<\/span> <span class=\"caps\">IP<\/span><\/span><\/a>&nbsp;offers a micro-bump array that adhe\u00adres to the <span class=\"caps\">JEDEC<\/span> <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">SDRAM<\/span> stan\u00addard for the shor\u00adtest pos\u00adsi\u00adble 2.<span class=\"caps\">5D<\/span> packa\u00adge rou\u00adtes and hig\u00adhest signal integrity.<\/p>\n<p>With an aggre\u00adga\u00adted band\u00adwidth of 409 giga\u00adbytes per second, the <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">PHY<\/span> deli\u00advers the requi\u00adred mas\u00adsi\u00adve com\u00adpu\u00adte per\u00adfor\u00admance of sys\u00adtem-on-chips (SoCs) in advan\u00adced Fin\u00adFET pro\u00adces\u00adses. The <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">IP<\/span> is part of Syn\u00adop\u00adsys\u2019 com\u00adpre\u00adhen\u00adsi\u00adve memo\u00adry inter\u00adface <span class=\"caps\">IP<\/span> solu\u00adti\u00adon that includes <span class=\"caps\">DDR5<\/span>\/4\/3\/2 and <span class=\"caps\">LPDDR5<\/span>\/4\/3\/2 <span class=\"caps\">IP<\/span>, which have been vali\u00adda\u00adted in hundreds of designs and ship\u00adped in mil\u00adli\u00adons of&nbsp;SoCs.<\/p>\n<p><span class=\"dquo\">\u201c<\/span>As a lea\u00adding glo\u00adbal semi\u00adcon\u00adduc\u00adtor manu\u00adfac\u00adtu\u00adrer, <span class=\"caps\">SK<\/span> hynix makes signi\u00adfi\u00adcant invest\u00adments in deve\u00adlo\u00adping robust DRAMs that offer increased capa\u00adci\u00adty and pro\u00adces\u00adsing speed while main\u00adtai\u00adning strict qua\u00adli\u00adty con\u00adtrol,\u201d said&nbsp;<span class=\"xn-person\">Jun Hyun Chun<\/span>, seni\u00ador vice pre\u00adsi\u00addent, <span class=\"caps\">HBM<\/span> Pro\u00adduct Cham\u00adpi\u00adon and Head of <span class=\"caps\">DRAM<\/span> Design at <span class=\"caps\">SK<\/span> hynix. \u201cWe con\u00adti\u00adnue to col\u00adla\u00adbo\u00adra\u00adte with Syn\u00adop\u00adsys to pro\u00advi\u00adde cus\u00adto\u00admers with a high-per\u00adfor\u00admance <span class=\"caps\">HBM<\/span> <span class=\"caps\">DRAM<\/span> solu\u00adti\u00adon that is ful\u00adly-tes\u00adted and inter\u00adope\u00adra\u00adble with Syn\u00adop\u00adsys\u2019 Design\u00adWa\u00adre <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">IP<\/span>, which deli\u00advers the requi\u00adred capa\u00adci\u00adty, through\u00adput and power of com\u00adpu\u00adte-inten\u00adsi\u00adve SoCs in advan\u00adced processes.\u201d&nbsp;<\/p>\n<p><span class=\"dquo\">\u201c<\/span><span class=\"caps\">TSMC<\/span>\u2019s long histo\u00adry of suc\u00adcessful col\u00adla\u00adbo\u00adra\u00adti\u00adon with Syn\u00adop\u00adsys has pro\u00advi\u00added our mutu\u00adal cus\u00adto\u00admers with access to a broad port\u00adfo\u00adlio of high-qua\u00adli\u00adty Design\u00adWa\u00adre <span class=\"caps\">IP<\/span> on <span class=\"caps\">TSMC<\/span>\u2019s advan\u00adced pro\u00adcess tech\u00adno\u00adlo\u00adgies, which they can inte\u00adgra\u00adte into their high-per\u00adfor\u00admance SoCs for a wide ran\u00adge of appli\u00adca\u00adti\u00adons,\u201d said&nbsp;<span class=\"xn-person\">Suk Lee<\/span>, seni\u00ador direc\u00adtor of the Design Infra\u00adstruc\u00adtu\u00adre Manage\u00adment Divi\u00adsi\u00adon at <span class=\"caps\">TSMC<\/span>. \u201c<span class=\"caps\">TSMC<\/span>\u2019s indus\u00adtry-lea\u00adding <span class=\"caps\">N7<\/span> pro\u00adcess and CoWoS<sup>\u00ae<\/sup>&nbsp;pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgies com\u00adbi\u00adned with Syn\u00adop\u00adsys\u2019 sili\u00adcon-pro\u00adven Design\u00adWa\u00adre <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">IP<\/span> allows desi\u00adgners to achie\u00adve fas\u00adter sili\u00adcon-to-packa\u00adge manu\u00adfac\u00adtu\u00adring with impro\u00adved yield, while mini\u00admi\u00adzing inte\u00adgra\u00adti\u00adon&nbsp;risk.\u201d<\/p>\n<p><span class=\"dquo\">\u201c<\/span>High-per\u00adfor\u00admance com\u00adpu\u00adting SoCs are requi\u00adring signi\u00adfi\u00adcant\u00adly more memo\u00adry band\u00adwidth to mana\u00adge the mas\u00adsi\u00adve amounts of data trans\u00adfer to sup\u00adport rich gra\u00adphics and machi\u00adne lear\u00adning workloads,\u201d said&nbsp;<span class=\"xn-person\">John Koe\u00adter<\/span>, seni\u00ador vice pre\u00adsi\u00addent of mar\u00adke\u00adting and stra\u00adtegy for <span class=\"caps\">IP<\/span> at Syn\u00adop\u00adsys. \u201cAs the lea\u00adding memo\u00adry inter\u00adface <span class=\"caps\">IP<\/span> pro\u00advi\u00adder, Syn\u00adop\u00adsys deli\u00advers a ran\u00adge of sili\u00adcon-pro\u00adven Design\u00adWa\u00adre Memo\u00adry Inter\u00adface <span class=\"caps\">IP<\/span> solu\u00adti\u00adons with lea\u00adding power, per\u00adfor\u00admance, and area to address the most chal\u00adlen\u00adging through\u00adput requirements.\u201d&nbsp;<\/p>\n<p><b>Avai\u00adla\u00adbi\u00adli\u00adty <span class=\"amp\">&amp;<\/span> Resources<\/b><\/p>\n<p>The Syn\u00adop\u00adsys Design\u00adWa\u00adre <span class=\"caps\">HBM2<\/span>\/<span class=\"caps\">2E<\/span> <span class=\"caps\">IP<\/span> is available now.<br>\nFor more infor\u00adma\u00adti\u00adon,&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=2729407-1&amp;h=1617832099&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fdw%2Fipdir.php%3Fds%3Ddwc_hbm2&amp;a=visit+the+DesignWare+HBM+IP+web+page\" target=\"_blank\" rel=\"nofollow noopener noreferrer\">visit the Design\u00adWa\u00adre <span class=\"caps\">HBM<\/span> <span class=\"caps\">IP<\/span> web page<\/a>.<\/p>\n<p><b>About Design\u00adWa\u00adre&nbsp;<span class=\"caps\">IP<\/span><\/b><\/p>\n<p>Syn\u00adop\u00adsys is a lea\u00adding pro\u00advi\u00adder of high-qua\u00adli\u00adty, sili\u00adcon-pro\u00adven <span class=\"caps\">IP<\/span> solu\u00adti\u00adons for SoC designs. The broad Design\u00adWa\u00adre <span class=\"caps\">IP<\/span> port\u00adfo\u00adlio includes logic libra\u00adri\u00ades, embedded memo\u00adries, embedded test, ana\u00adlog <span class=\"caps\">IP<\/span>, wired and wire\u00adless inter\u00adface <span class=\"caps\">IP<\/span>, secu\u00adri\u00adty <span class=\"caps\">IP<\/span>, embedded pro\u00adces\u00adsors, and sub\u00adsys\u00adtems. To acce\u00adle\u00adra\u00adte pro\u00adto\u00adty\u00adp\u00ading, soft\u00adware deve\u00adlo\u00adp\u00adment, and inte\u00adgra\u00adti\u00adon of <span class=\"caps\">IP<\/span> into SoCs, Syn\u00adop\u00adsys\u2019 <span class=\"caps\">IP<\/span> Acce\u00adle\u00adra\u00adted initia\u00adti\u00adve offers <span class=\"caps\">IP<\/span> pro\u00adto\u00adty\u00adp\u00ading kits, <span class=\"caps\">IP<\/span> soft\u00adware deve\u00adlo\u00adp\u00adment kits, and <span class=\"caps\">IP<\/span> sub\u00adsys\u00adtems. Syn\u00adop\u00adsys\u2019 exten\u00adsi\u00adve invest\u00adment in <span class=\"caps\">IP<\/span> qua\u00adli\u00adty, com\u00adpre\u00adhen\u00adsi\u00adve tech\u00adni\u00adcal sup\u00adport, and robust <span class=\"caps\">IP<\/span> deve\u00adlo\u00adp\u00adment metho\u00addo\u00adlo\u00adgy enable desi\u00adgners to redu\u00adce inte\u00adgra\u00adti\u00adon risk and acce\u00adle\u00adra\u00adte time-to-mar\u00adket. For more infor\u00adma\u00adti\u00adon on Design\u00adWa\u00adre <span class=\"caps\">IP<\/span>, visit&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=2729407-1&amp;h=884554537&amp;u=http%3A%2F%2Fwww.synopsys.com%2Fdesignware&amp;a=http%3A%2F%2Fwww.synopsys.com%2Fdesignware\" target=\"_blank\" rel=\"nofollow noopener noreferrer\">http:\/\/www.synopsys.com\/designware<\/a>.<\/p>\n<p><b>About Syn\u00adop\u00adsys<\/b><\/p>\n<p>Syn\u00adop\u00adsys, Inc. (Nasdaq: <span class=\"caps\">SNPS<\/span>) is the Sili\u00adcon to Soft\u00adware<sup>\u2122<\/sup>&nbsp;part\u00adner for inno\u00adva\u00adti\u00adve com\u00adpa\u00adnies deve\u00adlo\u00adping the elec\u00adtro\u00adnic pro\u00adducts and soft\u00adware appli\u00adca\u00adti\u00adons we rely on every day. As the world\u2019s 15th lar\u00adgest soft\u00adware com\u00adpa\u00adny, Syn\u00adop\u00adsys has a long histo\u00adry of being a glo\u00adbal lea\u00adder in elec\u00adtro\u00adnic design auto\u00adma\u00adti\u00adon (<span class=\"caps\">EDA<\/span>) and semi\u00adcon\u00adduc\u00adtor <span class=\"caps\">IP<\/span> and is also gro\u00adwing its lea\u00adder\u00adship in soft\u00adware secu\u00adri\u00adty and qua\u00adli\u00adty solu\u00adti\u00adons. Whe\u00adther you\u2019\u00adre a sys\u00adtem-on-chip (SoC) desi\u00adgner crea\u00adting advan\u00adced semi\u00adcon\u00adduc\u00adtors, or a soft\u00adware deve\u00adlo\u00adper wri\u00adting appli\u00adca\u00adti\u00adons that requi\u00adre the hig\u00adhest secu\u00adri\u00adty and qua\u00adli\u00adty, Syn\u00adop\u00adsys has the solu\u00adti\u00adons nee\u00added to deli\u00adver inno\u00adva\u00adti\u00adve, high-qua\u00adli\u00adty, secu\u00adre pro\u00adducts. Learn more at&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=2729407-1&amp;h=610654470&amp;u=https%3A%2F%2Fwww.synopsys.com%2F&amp;a=www.synopsys.com\" target=\"_blank\" rel=\"nofollow noopener noreferrer\">www.synopsys.com<\/a>.<\/p>\n<p><b>Edi\u00adto\u00adri\u00adal Contact:<br>\n<\/b><span class=\"xn-person\">Kel\u00adly&nbsp;James<\/span><br>\nSyn\u00adop\u00adsys,&nbsp;Inc.<br>\n650\u2013584-8972<br>\n<a href=\"mailto:kellyj@synopsys.com\" target=\"_blank\" rel=\"nofollow noopener noreferrer\">kellyj@synopsys.com<\/a><b>&nbsp;<\/b><\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>Design\u00adWa\u00adre <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">PHY<\/span> <span class=\"caps\">IP<\/span> in <span class=\"caps\">TSMC<\/span>\u2019s <span class=\"caps\">N7<\/span> Pro\u00adcess Deli\u00advers High Through\u00adput for Advan\u00adced Gra\u00adphics, High-Per\u00ad\u00adfor\u00ad\u00admance Com\u00adpu\u00adting and Net\u00adwor\u00adking&nbsp;SoCs &nbsp; <span class=\"caps\">MOUNTAIN<\/span> <span class=\"caps\">VIEW<\/span>, Calif.,&nbsp;Feb. 25, 2020&nbsp;\/PRNews\u00adwire\/ \u2013 High\u00adlights: Syn\u00adop\u00adsys\u2019 Design\u00adWa\u00adre <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">IP<\/span> in <span class=\"caps\">TSMC<\/span>\u2019s <span class=\"caps\">N7<\/span> pro\u00adcess pro\u00advi\u00addes up to 409&nbsp;GBps&nbsp;aggre\u00adga\u00adte memo\u00adry band\u00adwidth with low-power con\u00adsump\u00adti\u00adon and laten\u00adcy The <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">PHY<\/span> has been veri\u00adfied using <span class=\"caps\">TSMC<\/span>\u2019s CoWoS\u00ae tech\u00adno\u00adlo\u00adgy (\u2026) <a class=\"moretag\" href=\"https:\/\/www.planet3dnow.de\/cms\/55319-synopsys-delivers-silicon-proven-hbm2e-phy-ip-operating-at-3-2-gbps\/\">Wei\u00adter\u00adle\u00adsen&nbsp;\u00bb<\/a><\/p>\n","protected":false},"author":593,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[1816,2275,1037],"class_list":["post-55319","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","tag-hbm2e","tag-synopsys","tag-tsmc","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/55319","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/593"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=55319"}],"version-history":[{"count":1,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/55319\/revisions"}],"predecessor-version":[{"id":55320,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/55319\/revisions\/55320"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=55319"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=55319"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=55319"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}