{"id":55633,"date":"2020-03-10T18:58:39","date_gmt":"2020-03-10T17:58:39","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=55633"},"modified":"2020-03-10T18:58:39","modified_gmt":"2020-03-10T17:58:39","slug":"xilinx-announces-worlds-highest-bandwidth-highest-compute-density-adaptable-platform-for-network-and-cloud-acceleration","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/55633-xilinx-announces-worlds-highest-bandwidth-highest-compute-density-adaptable-platform-for-network-and-cloud-acceleration\/","title":{"rendered":"Xilinx Announces World\u2019s Highest Bandwidth, Highest Compute Density Adaptable Platform for Network and Cloud Acceleration"},"content":{"rendered":"

SAN<\/span> JOSE<\/span>, Calif.<\/span>, March 10, 2020<\/span> \/PRNewswire\/ \u2014 Xilinx, Inc. (NASDAQ<\/span>: XLNX<\/span>) today announ\u00adced Ver\u00adsal\u2122<\/sup> Pre\u00admi\u00adum, the third series in the Ver\u00adsal ACAP<\/span><\/a> port\u00adfo\u00adlio. The Ver\u00adsal Pre\u00admi\u00adum<\/a> series fea\u00adtures high\u00adly inte\u00adgra\u00adted, net\u00adwork\u00aded and power-opti\u00admi\u00adzed cores and the industry\u2019s hig\u00adhest band\u00adwidth and com\u00adpu\u00adte den\u00adsi\u00adty on an adap\u00adta\u00adble plat\u00adform. Ver\u00adsal Pre\u00admi\u00adum is desi\u00adgned for the hig\u00adhest band\u00adwidth net\u00adworks ope\u00adra\u00adting in ther\u00admal\u00adly and spa\u00adti\u00adal\u00adly cons\u00adtrai\u00adned envi\u00adron\u00adments, as well as for cloud pro\u00advi\u00adders who need sca\u00adlable, adap\u00adta\u00adble appli\u00adca\u00adti\u00adon acceleration.<\/p>\n

<\/a><\/p>\n

Ver\u00adsal is the industry\u2019s first adap\u00adti\u00adve com\u00adpu\u00adte acce\u00adle\u00adra\u00adti\u00adon plat\u00adform (ACAP<\/span><\/a>), a revo\u00adlu\u00adtio\u00adna\u00adry new cate\u00adgo\u00adry of hete\u00adro\u00adge\u00adneous com\u00adpu\u00adte devices with capa\u00adbi\u00adli\u00adties that far exceed tho\u00adse of con\u00adven\u00adtio\u00adnal sili\u00adcon archi\u00adtec\u00adtures. Deve\u00adlo\u00adped on TSMC<\/span>\u2019s 7\u2011nanometer pro\u00adcess tech\u00adno\u00adlo\u00adgy, Ver\u00adsal Pre\u00admi\u00adum com\u00adbi\u00adnes soft\u00adware pro\u00adgramma\u00adbi\u00adli\u00adty with dyna\u00admi\u00adcal\u00adly con\u00adfi\u00adgura\u00adble hard\u00adware acce\u00adle\u00adra\u00adti\u00adon and pre-engi\u00adnee\u00adred con\u00adnec\u00adti\u00advi\u00adty and secu\u00adri\u00adty fea\u00adtures to enable a fas\u00adter time-to-mar\u00adket. The Ver\u00adsal Pre\u00admi\u00adum series deli\u00advers up to 3X<\/span> hig\u00adher through\u00adput com\u00adpared to cur\u00adrent gene\u00adra\u00adti\u00adon FPGAs, with built-in Ether\u00adnet, Inter\u00adla\u00adken, and cryp\u00adto\u00adgra\u00adphic engi\u00adnes that enable fast and secu\u00adre net\u00adworks. The series dou\u00adbles the com\u00adpu\u00adte den\u00adsi\u00adty of curr\u00adent\u00adly deploy\u00aded main\u00adstream FPGAs and pro\u00advi\u00addes the adap\u00adta\u00adbi\u00adli\u00adty to keep pace with incre\u00adasing\u00adly diver\u00adse and evol\u00adving cloud and net\u00adwor\u00adking workloads.<\/p>\n

\u201c<\/span>The Ver\u00adsal Pre\u00admi\u00adum series takes ACAPs to the next level deli\u00adve\u00adring breakth\u00adrough net\u00adwork\u00aded hard IP<\/span> inte\u00adgra\u00adti\u00adon enab\u00adling the deve\u00adlo\u00adp\u00adment of sin\u00adgle chip 400G<\/span> and 800G<\/span> solu\u00adti\u00adons,\u201d said Kirk Saban<\/span>, vice pre\u00adsi\u00addent of Pro\u00adduct and Plat\u00adform Mar\u00adke\u00adting at Xilinx. \u201cTar\u00adge\u00adting next-gene\u00adra\u00adti\u00adon net\u00adworks and cloud deploy\u00adments, Ver\u00adsal Pre\u00admi\u00adum deli\u00advers supe\u00adri\u00ador band\u00adwidth and com\u00adpu\u00adte den\u00adsi\u00adty in a sca\u00adlable plat\u00adform that is rea\u00addi\u00adly pro\u00adgramma\u00adble by hard\u00adware and soft\u00adware deve\u00adlo\u00adpers ali\u00adke for opti\u00admi\u00adzed acce\u00adle\u00adra\u00adti\u00adon and redu\u00adced TCO<\/span>.\u201d<\/p>\n

The Ver\u00adsal Pre\u00admi\u00adum series is built on a foun\u00adda\u00adti\u00adon of the curr\u00adent\u00adly ship\u00adping Ver\u00adsal AI<\/span> Core<\/a> and Ver\u00adsal Prime<\/a> ACAP<\/span> series. New and uni\u00adque to Ver\u00adsal Pre\u00admi\u00adum are 112Gbps PAM4<\/span> trans\u00adcei\u00advers, mul\u00adti-hundred giga\u00adbit Ether\u00adnet and Inter\u00adla\u00adken con\u00adnec\u00adti\u00advi\u00adty, high-speed cryp\u00adto\u00adgra\u00adphy, and PCIe\u00ae<\/sup> Gen5 with built-in DMA<\/span>, sup\u00adport\u00ading both CCIX<\/span> and CXL<\/span>. Tog\u00ade\u00adther with the Vitis\u2122<\/sup> uni\u00adfied soft\u00adware plat\u00adform<\/a> and Viv\u00ada\u00addo\u00ae<\/sup> Design Suite<\/a>, the Ver\u00adsal Pre\u00admi\u00adum series offers a com\u00adple\u00adte solu\u00adti\u00adon stack for hard\u00adware and soft\u00adware deve\u00adlo\u00adpers for maxi\u00admum productivity.<\/p>\n

Fas\u00adter, More Secu\u00adre Networks<\/b><\/p>\n

Great\u00adly increased net\u00adwork traf\u00adfic from 5G<\/span> net\u00adwork roll\u00adout is dri\u00adving demand for power-opti\u00admi\u00adzed through\u00adput and com\u00adpu\u00adte den\u00adsi\u00adty within the exis\u00adting foot\u00adprint and power enve\u00adlo\u00adpes. The Ver\u00adsal Pre\u00admi\u00adum series addres\u00adses the\u00adse chal\u00adlenges by deli\u00adve\u00adring up to 9Tb\/s of sca\u00adlable, adap\u00adta\u00adble seri\u00adal band\u00adwidth. This is achie\u00adved by uti\u00adli\u00adzing 112G<\/span> PAM4<\/span> trans\u00adcei\u00advers and inte\u00adgra\u00adted con\u00adnec\u00adti\u00advi\u00adty for core, metro and data cen\u00adter inter\u00adcon\u00adnect (DCI<\/span>) infra\u00adstruc\u00adtu\u00adre that dou\u00adbles band\u00adwidth den\u00adsi\u00adty per port and redu\u00adce laten\u00adcy by up to 50 percent.<\/p>\n

The pre-engi\u00adnee\u00adred con\u00adnec\u00adti\u00advi\u00adty enables secu\u00adre, mul\u00adti-tera\u00adbit Ether\u00adnet with the fle\u00adxi\u00adbi\u00adli\u00adty to sup\u00adport a varie\u00adty of data rates and pro\u00adto\u00adcols. Chan\u00adne\u00adli\u00adzed Ether\u00adnet cores deli\u00adver up to 5Tb\/s of through\u00adput in a mini\u00admi\u00adzed foot\u00adprint and high-speed cryp\u00adto\u00adgra\u00adphy engi\u00adnes pro\u00advi\u00adde up to 1.6Tb\/s of encrypt\u00aded line-rate through\u00adput and sup\u00adport for AES-GCM-256<\/span>\/128, MAC\u00adsec, and IPsec.<\/p>\n

\u201c<\/span>As the demand on the core net\u00adwork con\u00adti\u00adnues to grow, the need for adap\u00adta\u00adble infra\u00adstruc\u00adtu\u00adre hard\u00adware great\u00adly increa\u00adses. The new Ver\u00adsal Pre\u00admi\u00adum ACAP<\/span> builds on Xilinx\u2019s port\u00adfo\u00adlio of high-per\u00adfor\u00admance and fle\u00adxi\u00adble pro\u00adducts for com\u00admu\u00adni\u00adca\u00adti\u00adons net\u00adworks,\u201d said Jim McGre\u00adgor<\/span>, prin\u00adci\u00adpal ana\u00adlyst, TIRIAS<\/span> Rese\u00adarch. \u201cWith the inte\u00adgra\u00adti\u00adon of net\u00adwork\u00aded, power-opti\u00admi\u00adzed cores, Ver\u00adsal Pre\u00admi\u00adum will allow tel\u00adco ope\u00adra\u00adtors to build fast and secu\u00adre net\u00adworks while offe\u00adring adap\u00adta\u00adble acce\u00adle\u00adra\u00adti\u00adon for new data-inten\u00adsi\u00adve workloads that are trans\u00adforming net\u00adworks and data centers.\u201d<\/p>\n

Adap\u00adta\u00adble Cloud Acceleration<\/b><\/p>\n

The Ver\u00adsal Pre\u00admi\u00adum series is engi\u00adnee\u00adred to help hypers\u00adca\u00adlers reach the hig\u00adhest levels of acce\u00adle\u00adra\u00adti\u00adon for a wide ran\u00adge of data cen\u00adter workloads. The over 120TB<\/span>\/s of on-chip memo\u00adry band\u00adwidth, cou\u00adpled with the cus\u00adto\u00admizable memo\u00adry hier\u00adar\u00adchy, redu\u00adces data move\u00adment to remo\u00adve key bot\u00adt\u00adlen\u00adecks, while pre-engi\u00adnee\u00adred con\u00adnec\u00adti\u00advi\u00adty and cores allow drop-in inte\u00adgra\u00adti\u00adon into exis\u00adting cloud infra\u00adstruc\u00adtu\u00adre. From geno\u00admics, ana\u00adly\u00adtics and video trans\u00adco\u00adding to AI<\/span> infe\u00adrence for speech and image reco\u00adgni\u00adti\u00adon, Ver\u00adsal Pre\u00admi\u00adum deli\u00advers a high\u00adly inte\u00adgra\u00adted, cloud-rea\u00addy plat\u00adform enab\u00adling breakth\u00adrough per\u00adfor\u00admance for diver\u00adse workloads.<\/p>\n

Avai\u00adla\u00adbi\u00adli\u00adty<\/b><\/p>\n

The Ver\u00adsal Pre\u00admi\u00adum series will begin sam\u00adpling with ear\u00adly access cus\u00adto\u00admers in the first half of 2021. Docu\u00admen\u00adti\u00adon is curr\u00adent\u00adly available and cus\u00adto\u00admers can start pro\u00adto\u00adty\u00adp\u00ading now with the Ver\u00adsal Prime Eva\u00adlua\u00adti\u00adon Kit<\/a>. Ver\u00adsal Prime devices imple\u00adment many of the same archi\u00adtec\u00adtu\u00adral blocks as Ver\u00adsal Pre\u00admi\u00adum devices and sup\u00adport pin migra\u00adti\u00adon to Ver\u00adsal Premium.<\/p>\n

Visit our web\u00adsite for more infor\u00adma\u00adti\u00adon on Ver\u00adsal<\/a>, Ver\u00adsal Prime<\/a> series and the Ver\u00adsal AI<\/span> Core<\/a> series. For more infor\u00adma\u00adti\u00adon on Xilinx and its breakth\u00adrough tech\u00adno\u00adlo\u00adgies, plea\u00adse visit www.xilinx.com<\/a>.<\/p>\n

Fol\u00adlow Xilinx on Twit\u00adter<\/a>, Lin\u00adke\u00addIn<\/a> and Face\u00adbook<\/a>.<\/p>\n

About Xilinx
\n<\/b>Xilinx deve\u00adlo\u00adps high\u00adly fle\u00adxi\u00adble and adap\u00adti\u00adve pro\u00adces\u00adsing plat\u00adforms that enable rapid inno\u00adva\u00adti\u00adon across a varie\u00adty of tech\u00adno\u00adlo\u00adgies \u2013 from the end\u00adpoint to the edge to the cloud. Xilinx is the inven\u00adtor of the FPGA<\/span>, hard\u00adware pro\u00adgramma\u00adble SoCs, and the ACAP<\/span>, desi\u00adgned to deli\u00adver the most dyna\u00admic pro\u00adces\u00adsor tech\u00adno\u00adlo\u00adgy in the indus\u00adtry and enable the adap\u00adta\u00adble, intel\u00adli\u00adgent, and con\u00adnec\u00adted world of the future. For more infor\u00adma\u00adti\u00adon, visit www.xilinx.com<\/a>.<\/p>\n

\u00a9 Copy\u00adright 2020 Xilinx, Inc. Xilinx, the Xilinx logo and other desi\u00adgna\u00adted brands included her\u00adein are trade\u00admarks of Xilinx in the United Sta\u00adtes and other count\u00adries. PCI<\/span>, PCIe and PCI<\/span> Express are trade\u00admarks of PCI-SIG<\/span> and used under licen\u00adse. All other trade\u00admarks are pro\u00adper\u00adty of their respec\u00adti\u00adve owners.<\/i><\/p>\n

PR<\/span> Cont\u00adact:
\n<\/b>Bri\u00adan Garabedian<\/span>
\nbrian.garabedian@xilinx.com<\/a><\/p>\n

 <\/p>\n","protected":false},"excerpt":{"rendered":"

SAN<\/span> JOSE<\/span>, Calif., March 10, 2020 \/PRNewswire\/ \u2014 Xilinx, Inc. (NASDAQ<\/span>: XLNX<\/span>) today announ\u00adced Ver\u00adsal\u2122 Pre\u00admi\u00adum, the third series in the Ver\u00adsal ACAP<\/span> port\u00adfo\u00adlio. The Ver\u00adsal Pre\u00admi\u00adum series fea\u00adtures high\u00adly inte\u00adgra\u00adted, net\u00adwork\u00aded and power-opti\u00ad\u00admi\u00ad\u00adzed cores and the industry\u2019s hig\u00adhest band\u00adwidth and com\u00adpu\u00adte den\u00adsi\u00adty on an adap\u00adta\u00adble plat\u00adform. Ver\u00adsal Pre\u00admi\u00adum is desi\u00adgned for the hig\u00adhest band\u00adwidth net\u00adworks ope\u00adra\u00adting in ther\u00admal\u00adly and spa\u00adti\u00adal\u00adly cons\u00adtrai\u00adned (\u2026) Wei\u00adter\u00adle\u00adsen \u00bb<\/a><\/p>\n","protected":false},"author":593,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[2284,2283,1583],"class_list":["post-55633","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","tag-acap","tag-versal","tag-xilinx","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/55633","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/593"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=55633"}],"version-history":[{"count":1,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/55633\/revisions"}],"predecessor-version":[{"id":55635,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/55633\/revisions\/55635"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=55633"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=55633"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=55633"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}