{"id":58068,"date":"2020-08-26T11:43:27","date_gmt":"2020-08-26T09:43:27","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=58068"},"modified":"2020-08-26T11:43:27","modified_gmt":"2020-08-26T09:43:27","slug":"synopsys-and-tsmc-accelerate-2-5d-3dic-designs-with-cowos-s-and-integrated-fan-out-certified-design-flows","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/58068-synopsys-and-tsmc-accelerate-2-5d-3dic-designs-with-cowos-s-and-integrated-fan-out-certified-design-flows\/","title":{"rendered":"Synopsys and TSMC<\/span> Accelerate 2.5D<\/span>\/3DIC<\/span> Designs with CoWoS\u2011S and Integrated Fan-Out Certified Design Flows"},"content":{"rendered":"
\n

MOUNTAIN<\/span> VIEW<\/span>, Calif.<\/span>, Aug. 25, 2020<\/span> \u2014 Syn\u00adop\u00adsys, Inc.<\/a> announ\u00adced that Syn\u00adop\u00adsys and TSMC<\/span> have col\u00adla\u00adbo\u00adra\u00adted to deli\u00adver cer\u00adti\u00adfied design flows for advan\u00adced pack\u00ada\u00adging solu\u00adti\u00adons using the Syn\u00adop\u00adsys 3DIC<\/span> Com\u00adpi\u00adler<\/a> pro\u00adduct for both sili\u00adcon inter\u00adpo\u00adser based Chip-on-Wafer-on-Sub\u00adstra\u00adte (CoWoS\u2011S) and high-den\u00adsi\u00adty wafer-level RDL-based Inte\u00adgra\u00adted Fan-Out (InFO\u2011R) designs. 3DIC<\/span> Com\u00adpi\u00adler pro\u00advi\u00addes pack\u00ada\u00adging design solu\u00adti\u00adons requi\u00adred by today\u2019s com\u00adplex mul\u00adti-die sys\u00adtems for appli\u00adca\u00adti\u00adons like high-per\u00adfor\u00admance com\u00adpu\u00adting (HPC<\/span>), auto\u00admo\u00adti\u00adve and mobile.<\/p>\n<\/header>\n

\n

\u201c<\/span>Appli\u00adca\u00adti\u00adons such as AI<\/span> and 5G<\/span> net\u00adwor\u00adking incre\u00adasing\u00adly requi\u00adre hig\u00adher levels of inte\u00adgra\u00adti\u00adon, lower power con\u00adsump\u00adti\u00adon, smal\u00adler form fac\u00adtors, and fas\u00adter time to pro\u00adduc\u00adtion, and this is dri\u00adving the demand for advan\u00adced-pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgies,\u201d said Suk Lee<\/span>, seni\u00ador direc\u00adtor of the Design Infra\u00adstruc\u00adtu\u00adre Manage\u00adment Divi\u00adsi\u00adon at TSMC<\/span>. \u201cTSMC<\/span>\u2019s Inno\u00adva\u00adti\u00adve 3DIC<\/span> tech\u00adno\u00adlo\u00adgies such as CoWoS and InFO enable cus\u00adto\u00admer inno\u00adva\u00adti\u00adon with grea\u00adter func\u00adtion\u00ada\u00adli\u00adty and enhan\u00adced sys\u00adtem per\u00adfor\u00admance at incre\u00adasing\u00adly com\u00adpe\u00adti\u00adti\u00adve cos\u00adts. Our col\u00adla\u00adbo\u00adra\u00adti\u00adon with Syn\u00adop\u00adsys pro\u00advi\u00addes cus\u00adto\u00admers with a cer\u00adti\u00adfied solu\u00adti\u00adon for desig\u00adning with TSMC<\/span>\u2019s CoWoS and InFO pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgies to enable high pro\u00adduc\u00adti\u00advi\u00adty and fas\u00adter time to func\u00adtion\u00adal silicon.\u201d<\/p>\n

The Syn\u00adop\u00adsys 3DIC<\/span> Com\u00adpi\u00adler solu\u00adti\u00adon pro\u00advi\u00addes a uni\u00adfied chip-packa\u00adge co-design and ana\u00adly\u00adsis envi\u00adron\u00adment for crea\u00adting an opti\u00admal 2.5D<\/span>\/3D<\/span> mul\u00adti-die sys\u00adtem in a packa\u00adge. The solu\u00adti\u00adon includes fea\u00adtures such as TSMC<\/span> design macro sup\u00adport and auto-rou\u00adting of high-den\u00adsi\u00adty inter\u00adpo\u00adser based inter\u00adcon\u00adnects using CoWoS tech\u00adno\u00adlo\u00adgy. For RDL-based InFO designs, sche\u00addu\u00adles are redu\u00adced from months to a few weeks through auto\u00adma\u00adted DRC-awa\u00adre, all-ang\u00adle mul\u00adti\u00adlay\u00ader signal and power\/ground rou\u00adting, power\/ground pla\u00adne crea\u00adti\u00adon, and dum\u00admy metal inser\u00adti\u00adon, along with the sup\u00adport for TSMC<\/span> design macros.<\/p>\n

For CoWoS\u2011S and InFO\u2011R designs, dies need to be ana\u00adly\u00adzed in the con\u00adtext of the packa\u00adge and the over\u00adall sys\u00adtem.  Die-awa\u00adre packa\u00adge and packa\u00adge-awa\u00adre die power inte\u00adgri\u00adty, signal inte\u00adgri\u00adty, and ther\u00admal ana\u00adly\u00adsis are cri\u00adti\u00adcal for design vali\u00adda\u00adti\u00adon and sign\u00adoff. Inte\u00adgra\u00adti\u00adon of Ansys\u2019 Red\u00adHawk fami\u00adly of chip-packa\u00adge co-ana\u00adly\u00adsis solu\u00adti\u00adons in 3DIC<\/span> Com\u00adpi\u00adler meets this cri\u00adti\u00adcal need, enab\u00adling seam\u00adless ana\u00adly\u00adsis and fas\u00adter con\u00adver\u00adgence to an opti\u00admal solu\u00adti\u00adon. Cus\u00adto\u00admers can achie\u00adve smal\u00adler designs and hig\u00adher per\u00adfor\u00admance by eli\u00admi\u00adna\u00adting overdesign.<\/p>\n

\u201c<\/span>Syn\u00adop\u00adsys and TSMC<\/span> reco\u00adgni\u00adze the design chal\u00adlenges being faced by our cus\u00adto\u00admers loo\u00adking to crea\u00adte next-gene\u00adra\u00adti\u00adon pro\u00adducts using mul\u00adti-die solu\u00adti\u00adons, and our col\u00adla\u00adbo\u00adra\u00adti\u00adon pro\u00advi\u00addes our mutu\u00adal cus\u00adto\u00admers with an opti\u00admi\u00adzed path to imple\u00admen\u00adta\u00adti\u00adon,\u201d said Charles Mat\u00adar, seni\u00ador vice pre\u00adsi\u00addent of Sys\u00adtem Solu\u00adti\u00adons and Eco\u00adsys\u00adtem Ena\u00adblem\u00adent for the Design Group at Syn\u00adop\u00adsys. \u201cBy pro\u00advi\u00adding natively imple\u00admen\u00adted sili\u00adcon inter\u00adpo\u00adser and fan-out lay\u00adouts, phy\u00adsi\u00adcal veri\u00adfi\u00adca\u00adti\u00adon, co-simu\u00adla\u00adti\u00adon and ana\u00adly\u00adsis capa\u00adbi\u00adli\u00adties in a sin\u00adgle uni\u00adfied plat\u00adform, we enable our cus\u00adto\u00admers to address today\u2019s com\u00adplex archi\u00adtec\u00adtures and pack\u00ada\u00adging requi\u00adre\u00adments, in addi\u00adti\u00adon, to increased pro\u00adduc\u00adti\u00advi\u00adty and fas\u00adter tur\u00adn\u00adaround time.\u201d<\/p>\n

For more infor\u00adma\u00adti\u00adon, plea\u00adse visit Syn\u00adop\u00adsys\u2019 3DIC<\/span> Compiler\u2019s web\u00adpage at www.synopsys.com\/3DIC<\/span><\/a>.<\/p>\n

About Syn\u00adop\u00adsys
\n<\/b><\/p>\n

Syn\u00adop\u00adsys, Inc. is the Sili\u00adcon to Soft\u00adware\\<\/sup> part\u00adner for inno\u00adva\u00adti\u00adve com\u00adpa\u00adnies deve\u00adlo\u00adping the elec\u00adtro\u00adnic pro\u00adducts and soft\u00adware appli\u00adca\u00adti\u00adons we rely on every day. As the world\u2019s 15th lar\u00adgest soft\u00adware com\u00adpa\u00adny, Syn\u00adop\u00adsys has a long histo\u00adry of being a glo\u00adbal lea\u00adder in elec\u00adtro\u00adnic design auto\u00adma\u00adti\u00adon (EDA<\/span>) and semi\u00adcon\u00adduc\u00adtor IP<\/span> and is also gro\u00adwing its lea\u00adder\u00adship in soft\u00adware secu\u00adri\u00adty and qua\u00adli\u00adty solu\u00adti\u00adons. Whe\u00adther you\u2019re a sys\u00adtem-on-chip (SoC) desi\u00adgner crea\u00adting advan\u00adced semi\u00adcon\u00adduc\u00adtors, or a soft\u00adware deve\u00adlo\u00adper wri\u00adting appli\u00adca\u00adti\u00adons that requi\u00adre the hig\u00adhest secu\u00adri\u00adty and qua\u00adli\u00adty, Syn\u00adop\u00adsys has the solu\u00adti\u00adons nee\u00added to deli\u00adver inno\u00adva\u00adti\u00adve, high-qua\u00adli\u00adty, secu\u00adre pro\u00adducts. Learn more at www.synopsys.com<\/a><\/u>.<\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

MOUNTAIN<\/span> VIEW<\/span>, Calif., Aug. 25, 2020 \u2014 Syn\u00adop\u00adsys, Inc. announ\u00adced that Syn\u00adop\u00adsys and TSMC<\/span> have col\u00adla\u00adbo\u00adra\u00adted to deli\u00adver cer\u00adti\u00adfied design flows for advan\u00adced pack\u00ada\u00adging solu\u00adti\u00adons using the Syn\u00adop\u00adsys 3DIC<\/span> Com\u00adpi\u00adler pro\u00adduct for both sili\u00adcon inter\u00adpo\u00adser based Chip-on-Wafer-on-Sub\u00adstra\u00adte (CoWoS\u2011S) and high-den\u00adsi\u00adty wafer-level RDL-based Inte\u00adgra\u00adted Fan-Out (InFO\u2011R) designs. 3DIC<\/span> Com\u00adpi\u00adler pro\u00advi\u00addes pack\u00ada\u00adging design solu\u00adti\u00adons requi\u00adred by today\u2019s com\u00adplex mul\u00adti-die sys\u00adtems for appli\u00adca\u00adti\u00adons like high-per\u00adfor\u00admance com\u00adpu\u00adting (HPC<\/span>), auto\u00admo\u00adti\u00adve and mobile.<\/p>\n

\u201c<\/span>Appli\u00adca\u00adti\u00adons such as AI<\/span> and 5G<\/span> net\u00adwor\u00adking incre\u00adasing\u00adly requi\u00adre hig\u00adher levels of inte\u00adgra\u00adti\u00adon, lower power con\u00adsump\u00adti\u00adon, smal\u00adler form fac\u00adtors, and fas\u00adter time to pro\u00adduc\u00adtion, and this is dri\u00adving the demand for advan\u00adced-pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgies,\u201d said Suk Lee, seni\u00ador direc\u00adtor of the Design Infra\u00adstruc\u00adtu\u00adre Manage\u00adment Divi\u00adsi\u00adon at TSMC<\/span>. \u201cTSMC<\/span>\u2019s Inno\u00adva\u00adti\u00adve 3DIC<\/span> tech\u00adno\u00adlo\u00adgies such as CoWoS and InFO enable cus\u00adto\u00admer inno\u00adva\u00adti\u00adon with grea\u00adter func\u00adtion\u00ada\u00adli\u00adty and enhan\u00adced sys\u00adtem per\u00adfor\u00admance at incre\u00adasing\u00adly com\u00adpe\u00adti\u00adti\u00adve cos\u00adts. Our col\u00adla\u00adbo\u00adra\u00adti\u00adon with Syn\u00adop\u00adsys pro\u00advi\u00addes cus\u00adto\u00admers with a cer\u00adti\u00adfied solu\u00adti\u00adon for desig\u00adning with TSMC<\/span>\u2019s CoWoS and InFO pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgies to enable high pro\u00adduc\u00adti\u00advi\u00adty and fas\u00adter time to func\u00adtion\u00adal sili\u00adcon.\u201d (\u2026) Wei\u00adter\u00adle\u00adsen \u00bb<\/a><\/p>\n","protected":false},"author":593,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[2395,2396,2268,2275,1037],"class_list":["post-58068","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","tag-cowos-s","tag-info-r","tag-packaging","tag-synopsys","tag-tsmc","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/58068","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/593"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=58068"}],"version-history":[{"count":1,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/58068\/revisions"}],"predecessor-version":[{"id":58069,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/58068\/revisions\/58069"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=58068"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=58068"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=58068"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}