{"id":63606,"date":"2021-10-09T10:36:21","date_gmt":"2021-10-09T08:36:21","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=63606"},"modified":"2021-10-09T10:36:21","modified_gmt":"2021-10-09T08:36:21","slug":"synopsys-accelerates-multi-die-designs-with-industrys-first-complete-hbm3-ip-and-verification-solutions","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/63606-synopsys-accelerates-multi-die-designs-with-industrys-first-complete-hbm3-ip-and-verification-solutions\/","title":{"rendered":"Synopsys Accelerates Multi-Die Designs with Industry\u2019s First Complete <span class=\"caps\">HBM3<\/span> <span class=\"caps\">IP<\/span> and Verification Solutions"},"content":{"rendered":"<p><span class=\"caps\">HBM3<\/span> <span class=\"caps\">IP<\/span> Solu\u00adti\u00adon Deli\u00advers Maxi\u00admum Memo\u00adry Band\u00adwidth of 921 <span class=\"caps\">GB<\/span>\/s for High-Per\u00adfor\u00admance Com\u00adpu\u00adting, <span class=\"caps\">AI<\/span>, and Gra\u00adphics&nbsp;SoCs<\/p>\n<p><span class=\"xn-location\"><span class=\"caps\">MOUNTAIN<\/span> <span class=\"caps\">VIEW<\/span>, Calif.<\/span>,&nbsp;<span class=\"xn-chron\">Oct. 7, 2021<\/span>&nbsp;\/<a href=\"http:\/\/www.prnewswire.com\/\" target=\"_blank\" rel=\"noopener\">PRNews\u00adwire<\/a>\/ \u2013<\/p>\n<p><b>High\u00adlights of this Announcement:<\/b><\/p>\n<ul type=\"disc\">\n<li>The Design\u00adWa\u00adre <span class=\"caps\">HBM3<\/span> Con\u00adtrol\u00adler, <span class=\"caps\">PHY<\/span>, and Veri\u00adfi\u00adca\u00adti\u00adon <span class=\"caps\">IP<\/span> redu\u00adces inte\u00adgra\u00adti\u00adon risk and maxi\u00admi\u00adzes memo\u00adry per\u00adfor\u00admance in 2.<span class=\"caps\">5D<\/span> mul\u00adti-die systems<\/li>\n<li>Low-laten\u00adcy <span class=\"caps\">HBM3<\/span> Con\u00adtrol\u00adler with fle\u00adxi\u00adble con\u00adfi\u00adgu\u00adra\u00adti\u00adon opti\u00adons enhan\u00adce memo\u00adry bandwidth<\/li>\n<li>Pre-har\u00adden\u00aded or con\u00adfi\u00adgura\u00adble <span class=\"caps\">HBM3<\/span> <span class=\"caps\">PHY<\/span> in 5\u2011nm pro\u00adcess ope\u00adra\u00adtes at 7200 Mbps for up to <span class=\"caps\">2X<\/span> the data rate and impro\u00adves power effi\u00adci\u00aden\u00adcy by up to 60% com\u00adpared to&nbsp;<span class=\"caps\">HBM2E<\/span><\/li>\n<li>Veri\u00adfi\u00adca\u00adti\u00adon <span class=\"caps\">IP<\/span> and memo\u00adry models for ZeBu and <span class=\"caps\">HAPS<\/span> offer an end-to-end solu\u00adti\u00adon for rapid veri\u00adfi\u00adca\u00adti\u00adon clo\u00adsure from <span class=\"caps\">IP<\/span> to&nbsp;SoC<\/li>\n<li>Syn\u00adop\u00adsys\u2019 <span class=\"caps\">3DIC<\/span> Com\u00adpi\u00adler, an inte\u00adgra\u00adted mul\u00adti-die design and ana\u00adly\u00adsis plat\u00adform, pro\u00advi\u00addes a com\u00adpre\u00adhen\u00adsi\u00adve <span class=\"caps\">HBM3<\/span> auto-rou\u00adting solu\u00adti\u00adon for rapid and robust design development<\/li>\n<\/ul>\n<p><a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=711855638&amp;u=https%3A%2F%2Fwww.synopsys.com%2F&amp;a=Synopsys%2C+Inc.\" target=\"_blank\" rel=\"nofollow noopener\">Syn\u00adop\u00adsys, Inc.<\/a>&nbsp;(Nasdaq:&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=2384590654&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fcompany%2Finvestor-relations.html&amp;a=SNPS\" target=\"_blank\" rel=\"nofollow noopener\"><span class=\"caps\">SNPS<\/span><\/a>) today announ\u00adced the industry\u2019s first com\u00adple\u00adte <span class=\"caps\">HBM3<\/span> <span class=\"caps\">IP<\/span> solu\u00adti\u00adon, inclu\u00adding con\u00adtrol\u00adler, <span class=\"caps\">PHY<\/span>, and veri\u00adfi\u00adca\u00adti\u00adon <span class=\"caps\">IP<\/span> for 2.<span class=\"caps\">5D<\/span> mul\u00adti-die packa\u00adge sys\u00adtems. <span class=\"caps\">HBM3<\/span> tech\u00adno\u00adlo\u00adgy helps desi\u00adgners meet essen\u00adti\u00adal high-band\u00adwidth and low-power memo\u00adry requi\u00adre\u00adments for sys\u00adtem-on-chip (SoC) designs tar\u00adge\u00adting high-per\u00adfor\u00admance com\u00adpu\u00adting, <span class=\"caps\">AI<\/span> and gra\u00adphics appli\u00adca\u00adti\u00adons. Syn\u00adop\u00adsys\u2019&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=4133678396&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fdesignware-ip%2Finterface-ip%2Fhbm.html&amp;a=DesignWare%C2%AE+HBM3+Controller+and+PHY+IP\" target=\"_blank\" rel=\"nofollow noopener\">Design\u00adWa\u00adre\u00ae <span class=\"caps\">HBM3<\/span> Con\u00adtrol\u00adler and&nbsp;<span class=\"xn-person\"><span class=\"caps\">PHY<\/span> <span class=\"caps\">IP<\/span><\/span><\/a>, built on sili\u00adcon-pro\u00adven <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">IP<\/span>, levera\u00adge Syn\u00adop\u00adsys\u2019 inter\u00adpo\u00adser exper\u00adti\u00adse to pro\u00advi\u00adde a low-risk solu\u00adti\u00adon that enables high memo\u00adry band\u00adwidth at up to 921 <span class=\"caps\">GB<\/span>\/s.<\/p>\n<p>The Syn\u00adop\u00adsys veri\u00adfi\u00adca\u00adti\u00adon solu\u00adti\u00adon, inclu\u00adding&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=3378667508&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fverification%2Fverification-ip%2Fmemory%2Fhbm-verificationip.html&amp;a=Verification+IP\" target=\"_blank\" rel=\"nofollow noopener\">Veri\u00adfi\u00adca\u00adti\u00adon <span class=\"caps\">IP<\/span><\/a>&nbsp;with built-in covera\u00adge and veri\u00adfi\u00adca\u00adti\u00adon plans, off-the-shelf <span class=\"caps\">HBM3<\/span> memo\u00adry models for&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=934548234&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fverification%2Femulation%2Fzebu-server.html&amp;a=ZeBu%C2%AE+emulation\" target=\"_blank\" rel=\"nofollow noopener\">ZeBu\u00ae emu\u00adla\u00adti\u00adon<\/a>, and&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=2958631383&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fverification%2Fprototyping%2Fhaps.html&amp;a=HAPS%C2%AE+prototyping+system\" target=\"_blank\" rel=\"nofollow noopener\"><span class=\"caps\">HAPS<\/span>\u00ae pro\u00adto\u00adty\u00adp\u00ading sys\u00adtem<\/a>, acce\u00adle\u00adra\u00adtes veri\u00adfi\u00adca\u00adti\u00adon from <span class=\"caps\">HBM3<\/span> <span class=\"caps\">IP<\/span> to SoCs. To&nbsp;acce\u00adle\u00adra\u00adte&nbsp;deve\u00adlo\u00adp\u00adment of <span class=\"caps\">HBM3<\/span> sys\u00adtem designs, Syn\u00adop\u00adsys\u2019&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=1970097592&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fimplementation-and-signoff%2F3dic-design.html&amp;a=3DIC+Compiler\" target=\"_blank\" rel=\"nofollow noopener\"><span class=\"caps\">3DIC<\/span> Com\u00adpi\u00adler<\/a>&nbsp;mul\u00adti-die design plat\u00adform pro\u00advi\u00addes a ful\u00adly inte\u00adgra\u00adted archi\u00adtec\u00adtu\u00adral explo\u00adra\u00adti\u00adon, imple\u00admen\u00adta\u00adti\u00adon and sys\u00adtem-level ana\u00adly\u00adsis solution.<\/p>\n<p>Syn\u00adop\u00adsys\u2019 Design\u00adWa\u00adre <span class=\"caps\">HBM3<\/span> Con\u00adtrol\u00adler <span class=\"caps\">IP<\/span> sup\u00adports a varie\u00adty of HBM3-based sys\u00adtems with fle\u00adxi\u00adble con\u00adfi\u00adgu\u00adra\u00adti\u00adon opti\u00adons. The con\u00adtrol\u00adler mini\u00admi\u00adzes laten\u00adcy and opti\u00admi\u00adzes data inte\u00adgri\u00adty with advan\u00adced <span class=\"caps\">RAS<\/span> fea\u00adtures that include error cor\u00adrec\u00adtion code, refresh manage\u00adment and parity.<\/p>\n<p>The Design\u00adWa\u00adre <span class=\"caps\">HBM3<\/span>&nbsp;<span class=\"xn-person\"><span class=\"caps\">PHY<\/span> <span class=\"caps\">IP<\/span><\/span>&nbsp;in 5\u2011nm pro\u00adcess, available as pre-har\u00adden\u00aded or cus\u00adto\u00admer con\u00adfi\u00adgura\u00adble <span class=\"caps\">PHY<\/span>, ope\u00adra\u00adtes at up to 7200 Mbps per pin, signi\u00adfi\u00adcant\u00adly impro\u00adves power effi\u00adci\u00aden\u00adcy and sup\u00adports up to four acti\u00adve ope\u00adra\u00adting sta\u00adtes enab\u00adling dyna\u00admic fre\u00adquen\u00adcy sca\u00adling. The Design\u00adWa\u00adre <span class=\"caps\">HBM3<\/span> <span class=\"caps\">PHY<\/span> uti\u00adli\u00adzes an opti\u00admi\u00adzed micro bump array to help mini\u00admi\u00adze area. The sup\u00adport for inter\u00adpo\u00adser trace lengths gives desi\u00adgners more fle\u00adxi\u00adbi\u00adli\u00adty in the <span class=\"caps\">PHY<\/span> pla\u00adce\u00adment wit\u00adhout impac\u00adting performance.<\/p>\n<p>Syn\u00adop\u00adsys Veri\u00adfi\u00adca\u00adti\u00adon <span class=\"caps\">IP<\/span> for <span class=\"caps\">HBM3<\/span> uses next-gene\u00adra\u00adti\u00adon nati\u00adve Sys\u00adtem\u00adVer\u00adi\u00adlog Uni\u00adver\u00adsal Veri\u00adfi\u00adca\u00adti\u00adon Metho\u00addo\u00adlo\u00adgy archi\u00adtec\u00adtu\u00adre to ease inte\u00adgra\u00adti\u00adon of exis\u00adting veri\u00adfi\u00adca\u00adti\u00adon envi\u00adron\u00adments and run a grea\u00adter num\u00adber of tests, acce\u00adle\u00adra\u00adting time to first test. The off-the-shelf <span class=\"caps\">HBM3<\/span> memo\u00adry models for ZeBu emu\u00adla\u00adti\u00adon and <span class=\"caps\">HAPS<\/span> pro\u00adto\u00adty\u00adp\u00ading sys\u00adtem enable <span class=\"caps\">RTL<\/span> and soft\u00adware veri\u00adfi\u00adca\u00adti\u00adon for hig\u00adher levels of performance.<\/p>\n<p><span class=\"dquo\">\u201c<\/span>Syn\u00adop\u00adsys con\u00adti\u00adnues to address the design and veri\u00adfi\u00adca\u00adti\u00adon requi\u00adre\u00adments of data-inten\u00adsi\u00adve SoCs with high-qua\u00adli\u00adty memo\u00adry inter\u00adface <span class=\"caps\">IP<\/span> and veri\u00adfi\u00adca\u00adti\u00adon solu\u00adti\u00adons for the most advan\u00adced pro\u00adto\u00adcols like <span class=\"caps\">HBM3<\/span>, <span class=\"caps\">DDR5<\/span> and <span class=\"caps\">LPDDR5<\/span>,\u201d said&nbsp;<span class=\"xn-person\">John Koe\u00adter<\/span>, seni\u00ador vice pre\u00adsi\u00addent of mar\u00adke\u00adting and stra\u00adtegy for <span class=\"caps\">IP<\/span> at Syn\u00adop\u00adsys. \u201cThe com\u00adple\u00adte <span class=\"caps\">HBM3<\/span> <span class=\"caps\">IP<\/span> and veri\u00adfi\u00adca\u00adti\u00adon solu\u00adti\u00adons enable desi\u00adgners to meet incre\u00adasing band\u00adwidth, laten\u00adcy and power requi\u00adre\u00adments while acce\u00adle\u00adra\u00adting veri\u00adfi\u00adca\u00adti\u00adon clo\u00adsure, all from a sin\u00adgle, trus\u00adted provider.\u201d<\/p>\n<p>Syn\u00adop\u00adsys\u2019 broad Design\u00adWa\u00adre <span class=\"caps\">IP<\/span> port\u00adfo\u00adlio includes logic libra\u00adri\u00ades, embedded memo\u00adries, <span class=\"caps\">PVT<\/span> sen\u00adsors, embedded test, ana\u00adlog <span class=\"caps\">IP<\/span>, inter\u00adface <span class=\"caps\">IP<\/span>, secu\u00adri\u00adty <span class=\"caps\">IP<\/span>, embedded pro\u00adces\u00adsors and sub\u00adsys\u00adtems. To acce\u00adle\u00adra\u00adte pro\u00adto\u00adty\u00adp\u00ading, soft\u00adware deve\u00adlo\u00adp\u00adment and inte\u00adgra\u00adti\u00adon of <span class=\"caps\">IP<\/span> into SoCs, Syn\u00adop\u00adsys\u2019 <span class=\"caps\">IP<\/span> Acce\u00adle\u00adra\u00adted initia\u00adti\u00adve offers <span class=\"caps\">IP<\/span> pro\u00adto\u00adty\u00adp\u00ading kits, <span class=\"caps\">IP<\/span> soft\u00adware deve\u00adlo\u00adp\u00adment kits and <span class=\"caps\">IP<\/span> sub\u00adsys\u00adtems. Our exten\u00adsi\u00adve invest\u00adment in <span class=\"caps\">IP<\/span> qua\u00adli\u00adty and com\u00adpre\u00adhen\u00adsi\u00adve tech\u00adni\u00adcal sup\u00adport enable desi\u00adgners to redu\u00adce inte\u00adgra\u00adti\u00adon risk and acce\u00adle\u00adra\u00adte time-to-mar\u00adket. For more infor\u00adma\u00adti\u00adon, plea\u00adse visit&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=1162746810&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fdesignware&amp;a=https%3A%2F%2Fwww.synopsys.com%2Fdesignware\" target=\"_blank\" rel=\"nofollow noopener\">https:\/\/www.synopsys.com\/designware<\/a>.<\/p>\n<p><b>Sup\u00adport\u00ading Cus\u00adto\u00admer and Part\u00adner Quotes<\/b><\/p>\n<p><span class=\"dquo\">\u201c<\/span>Micron is com\u00admit\u00adted to empowe\u00adring the world\u2019s most advan\u00adced com\u00adpu\u00adting sys\u00adtems with the industry\u2019s hig\u00adhest per\u00adforming solu\u00adti\u00adons. <span class=\"caps\">HBM3<\/span> will deli\u00adver the memo\u00adry band\u00adwidth cri\u00adti\u00adcal to enab\u00adling the next gene\u00adra\u00adti\u00adon of high-per\u00adfor\u00admance com\u00adpu\u00adting and arti\u00adfi\u00adci\u00adal intel\u00adli\u00adgence sys\u00adtems,\u201d said&nbsp;<span class=\"xn-person\">Mark Mon\u00adtierth<\/span>, Micron vice pre\u00adsi\u00addent and gene\u00adral mana\u00adger of High-Per\u00adfor\u00admance Memo\u00adry and Net\u00adwor\u00adking. \u201cOur col\u00adla\u00adbo\u00adra\u00adti\u00adon with Syn\u00adop\u00adsys will acce\u00adle\u00adra\u00adte eco\u00adsys\u00adtem deve\u00adlo\u00adp\u00adment for ultra-high band\u00adwidth, ener\u00adgy-effi\u00adci\u00adent <span class=\"caps\">HBM3<\/span> pro\u00adducts with unpre\u00adce\u00adden\u00adted performance.\u201d<\/p>\n<p><span class=\"dquo\">\u201c<\/span>The data dri\u00adven era of com\u00adpu\u00adting and evo\u00adlu\u00adti\u00adon of <span class=\"caps\">AI<\/span>, <span class=\"caps\">HPC<\/span>, gra\u00adphics, and other appli\u00adca\u00adti\u00adons have increased memo\u00adry band\u00adwidth requi\u00adre\u00adments expo\u00adnen\u00adti\u00adal\u00adly,\u201d said&nbsp;<span class=\"xn-person\">Kwan\u00adgil Park<\/span>, seni\u00ador vice pre\u00adsi\u00addent of Memo\u00adry Pro\u00adduct Plan\u00adning at Sam\u00adsung Elec\u00adtro\u00adnics. \u201cAs the world\u2019s lea\u00adding memo\u00adry chip maker, Sam\u00adsung is con\u00adti\u00adnu\u00adal\u00adly focu\u00adsed on sup\u00adport\u00ading eco\u00adsys\u00adtem rea\u00addi\u00adness and deve\u00adlo\u00adping <span class=\"caps\">HBM<\/span> to satis\u00adfy the gro\u00adwing band\u00adwidth requi\u00adre\u00adments across all appli\u00adca\u00adti\u00adons. Syn\u00adop\u00adsys is an eco\u00adsys\u00adtem pio\u00adneer in the <span class=\"caps\">HBM<\/span> indus\u00adtry and a valued part\u00adner. We look for\u00adward to con\u00adti\u00adnuing to pro\u00advi\u00adde the best <span class=\"caps\">HBM<\/span> per\u00adfor\u00admance to our customers.\u201d<\/p>\n<p><span class=\"dquo\">\u201c<\/span><span class=\"caps\">SK<\/span> hynix, a lea\u00adding glo\u00adbal semi\u00adcon\u00adduc\u00adtor manu\u00adfac\u00adtu\u00adrer, con\u00adti\u00adnues to invest in deve\u00adlo\u00adping next-gene\u00adra\u00adti\u00adon memo\u00adry tech\u00adno\u00adlo\u00adgies, inclu\u00adding <span class=\"caps\">HBM3<\/span> DRAMs, to meet the expo\u00adnen\u00adti\u00adal growth in workloads for <span class=\"caps\">AI<\/span> and gra\u00adphics appli\u00adca\u00adti\u00adons,\u201d said&nbsp;<span class=\"xn-person\">Cheol Kyu Park<\/span>, vice pre\u00adsi\u00addent, <span class=\"caps\">HBM<\/span> Pro\u00adduct Cham\u00adpi\u00adon and Head of <span class=\"caps\">DRAM<\/span> Pro\u00adduct Engi\u00adnee\u00adring at <span class=\"caps\">SK<\/span> hynix. \u201cWe will levera\u00adge our long-stan\u00adding rela\u00adti\u00adonship with Syn\u00adop\u00adsys to pro\u00advi\u00adde our mutu\u00adal cus\u00adto\u00admers with ful\u00adly-tes\u00adted and inter\u00adope\u00adra\u00adble <span class=\"caps\">HBM3<\/span> solu\u00adti\u00adons that can maxi\u00admi\u00adze memo\u00adry per\u00adfor\u00admance, capa\u00adci\u00adty and throughput.\u201d<\/p>\n<p><span class=\"dquo\">\u201c<\/span>Socionext, a glo\u00adbal lea\u00adder in SoC solu\u00adti\u00adons, tog\u00ade\u00adther with Syn\u00adop\u00adsys, an indus\u00adtry-lea\u00adding part\u00adner, pro\u00advi\u00adde com\u00adpre\u00adhen\u00adsi\u00adve solu\u00adti\u00adons to our cus\u00adto\u00admers across a wide ran\u00adge of mar\u00adkets,\u201d said&nbsp;<span class=\"xn-person\">Yuta\u00adka Haya\u00adshi<\/span>, vice pre\u00adsi\u00addent of Data Cen\u00adter <span class=\"amp\">&amp;<\/span> Net\u00adwor\u00adking Busi\u00adness Unit at Socionext. \u201cOur recent col\u00adla\u00adbo\u00adra\u00adti\u00adon with Syn\u00adop\u00adsys, lever\u00adaging Syn\u00adop\u00adsys\u2019 <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">IP<\/span> on 5\u2011nm pro\u00adcess and inte\u00adgra\u00adted full-sys\u00adtem mul\u00adti-die design plat\u00adform, will extend to include the new Design\u00adWa\u00adre <span class=\"caps\">HBM3<\/span> <span class=\"caps\">IP<\/span> and veri\u00adfi\u00adca\u00adti\u00adon solu\u00adti\u00adons. As a result, our cus\u00adto\u00admers can achie\u00adve hig\u00adher memo\u00adry per\u00adfor\u00admance and capa\u00adci\u00adty in SoCs requi\u00adring the upco\u00adming <span class=\"caps\">HBM3<\/span> specification.\u201d<\/p>\n<p><b>Avai\u00adla\u00adbi\u00adli\u00adty and Resources<\/b><\/p>\n<p>The Syn\u00adop\u00adsys&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=1127078931&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fdesignware-ip%2Finterface-ip%2Fhbm.html&amp;a=DesignWare+HBM3\" target=\"_blank\" rel=\"nofollow noopener\">Design\u00adWa\u00adre <span class=\"caps\">HBM3<\/span><\/a>&nbsp;Con\u00adtrol\u00adler, <span class=\"caps\">PHY<\/span>, and&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=3378667508&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fverification%2Fverification-ip%2Fmemory%2Fhbm-verificationip.html&amp;a=Verification+IP\" target=\"_blank\" rel=\"nofollow noopener\">Veri\u00adfi\u00adca\u00adti\u00adon <span class=\"caps\">IP<\/span><\/a>&nbsp;as well as the&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=248404311&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fverification%2Femulation%2Fzebu-server.html&amp;a=ZeBu+emulation\" target=\"_blank\" rel=\"nofollow noopener\">ZeBu emu\u00adla\u00adti\u00adon<\/a>&nbsp;memo\u00adry model,&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=1389547333&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fverification%2Fprototyping%2Fhaps.html&amp;a=HAPS+prototyping+system\" target=\"_blank\" rel=\"nofollow noopener\"><span class=\"caps\">HAPS<\/span> pro\u00adto\u00adty\u00adp\u00ading sys\u00adtem<\/a>, and&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=1970097592&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fimplementation-and-signoff%2F3dic-design.html&amp;a=3DIC+Compiler\" target=\"_blank\" rel=\"nofollow noopener\"><span class=\"caps\">3DIC<\/span> Com\u00adpi\u00adler<\/a>&nbsp;are available now.<\/p>\n<p><b>About Syn\u00adop\u00adsys<\/b><\/p>\n<p>Syn\u00adop\u00adsys, Inc. (Nasdaq: <span class=\"caps\">SNPS<\/span>) is the Sili\u00adcon to Soft\u00adware\u2122 part\u00adner for inno\u00adva\u00adti\u00adve com\u00adpa\u00adnies deve\u00adlo\u00adping the elec\u00adtro\u00adnic pro\u00adducts and soft\u00adware appli\u00adca\u00adti\u00adons we rely on every day. As an S<span class=\"amp\">&amp;<\/span>P 500 com\u00adpa\u00adny, Syn\u00adop\u00adsys has a long histo\u00adry of being a glo\u00adbal lea\u00adder in elec\u00adtro\u00adnic design auto\u00adma\u00adti\u00adon (<span class=\"caps\">EDA<\/span>) and semi\u00adcon\u00adduc\u00adtor <span class=\"caps\">IP<\/span> and offers the industry\u2019s broa\u00addest port\u00adfo\u00adlio of appli\u00adca\u00adti\u00adon secu\u00adri\u00adty test\u00ading tools and ser\u00advices. Whe\u00adther you\u2019\u00adre a sys\u00adtem-on-chip (SoC) desi\u00adgner crea\u00adting advan\u00adced semi\u00adcon\u00adduc\u00adtors, or a soft\u00adware deve\u00adlo\u00adper wri\u00adting more secu\u00adre, high-qua\u00adli\u00adty code, Syn\u00adop\u00adsys has the solu\u00adti\u00adons nee\u00added to deli\u00adver inno\u00adva\u00adti\u00adve pro\u00adducts. Learn more at&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=2094420931&amp;u=http%3A%2F%2Fwww.synopsys.com%2F&amp;a=www.synopsys.com\" target=\"_blank\" rel=\"nofollow noopener\">www.synopsys.com<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p><span class=\"caps\">HBM3<\/span> <span class=\"caps\">IP<\/span> Solu\u00adti\u00adon Deli\u00advers Maxi\u00admum Memo\u00adry Band\u00adwidth of 921 <span class=\"caps\">GB<\/span>\/s for High-Per\u00adfor\u00admance Com\u00adpu\u00adting, <span class=\"caps\">AI<\/span>, and Gra\u00adphics&nbsp;SoCs<\/p>\n<p><span class=\"xn-location\"><span class=\"caps\">MOUNTAIN<\/span> <span class=\"caps\">VIEW<\/span>, Calif.<\/span>,&nbsp;<span class=\"xn-chron\">Oct. 7, 2021<\/span>&nbsp;\/<a href=\"http:\/\/www.prnewswire.com\/\" target=\"_blank\" rel=\"noopener\">PRNews\u00adwire<\/a>\/ \u2013<\/p>\n<p><b>High\u00adlights of this Announcement:<\/b><\/p>\n<ul type=\"disc\">\n<li>The Design\u00adWa\u00adre <span class=\"caps\">HBM3<\/span> Con\u00adtrol\u00adler, <span class=\"caps\">PHY<\/span>, and Veri\u00adfi\u00adca\u00adti\u00adon <span class=\"caps\">IP<\/span> redu\u00adces inte\u00adgra\u00adti\u00adon risk and maxi\u00admi\u00adzes memo\u00adry per\u00adfor\u00admance in 2.<span class=\"caps\">5D<\/span> mul\u00adti-die systems<\/li>\n<li>Low-laten\u00adcy <span class=\"caps\">HBM3<\/span> Con\u00adtrol\u00adler with fle\u00adxi\u00adble con\u00adfi\u00adgu\u00adra\u00adti\u00adon opti\u00adons enhan\u00adce memo\u00adry bandwidth<\/li>\n<li>Pre-har\u00adden\u00aded or con\u00adfi\u00adgura\u00adble <span class=\"caps\">HBM3<\/span> <span class=\"caps\">PHY<\/span> in 5\u2011nm pro\u00adcess ope\u00adra\u00adtes at 7200 Mbps for up to <span class=\"caps\">2X<\/span> the data rate and impro\u00adves power effi\u00adci\u00aden\u00adcy by up to 60% com\u00adpared to&nbsp;<span class=\"caps\">HBM2E<\/span><\/li>\n<li>Veri\u00adfi\u00adca\u00adti\u00adon <span class=\"caps\">IP<\/span> and memo\u00adry models for ZeBu and <span class=\"caps\">HAPS<\/span> offer an end-to-end solu\u00adti\u00adon for rapid veri\u00adfi\u00adca\u00adti\u00adon clo\u00adsure from <span class=\"caps\">IP<\/span> to&nbsp;SoC<\/li>\n<li>Syn\u00adop\u00adsys\u2019 <span class=\"caps\">3DIC<\/span> Com\u00adpi\u00adler, an inte\u00adgra\u00adted mul\u00adti-die design and ana\u00adly\u00adsis plat\u00adform, pro\u00advi\u00addes a com\u00adpre\u00adhen\u00adsi\u00adve <span class=\"caps\">HBM3<\/span> auto-rou\u00adting solu\u00adti\u00adon for rapid and robust design development<\/li>\n<\/ul>\n<p><a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=711855638&amp;u=https%3A%2F%2Fwww.synopsys.com%2F&amp;a=Synopsys%2C+Inc.\" target=\"_blank\" rel=\"nofollow noopener\">Syn\u00adop\u00adsys, Inc.<\/a>&nbsp;(Nasdaq:&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=2384590654&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fcompany%2Finvestor-relations.html&amp;a=SNPS\" target=\"_blank\" rel=\"nofollow noopener\"><span class=\"caps\">SNPS<\/span><\/a>) today announ\u00adced the industry\u2019s first com\u00adple\u00adte <span class=\"caps\">HBM3<\/span> <span class=\"caps\">IP<\/span> solu\u00adti\u00adon, inclu\u00adding con\u00adtrol\u00adler, <span class=\"caps\">PHY<\/span>, and veri\u00adfi\u00adca\u00adti\u00adon <span class=\"caps\">IP<\/span> for 2.<span class=\"caps\">5D<\/span> mul\u00adti-die packa\u00adge sys\u00adtems. <span class=\"caps\">HBM3<\/span> tech\u00adno\u00adlo\u00adgy helps desi\u00adgners meet essen\u00adti\u00adal high-band\u00adwidth and low-power memo\u00adry requi\u00adre\u00adments for sys\u00adtem-on-chip (SoC) designs tar\u00adge\u00adting high-per\u00adfor\u00admance com\u00adpu\u00adting, <span class=\"caps\">AI<\/span> and gra\u00adphics appli\u00adca\u00adti\u00adons. Syn\u00adop\u00adsys\u2019&nbsp;<a href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3314171-1&amp;h=4133678396&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fdesignware-ip%2Finterface-ip%2Fhbm.html&amp;a=DesignWare%C2%AE+HBM3+Controller+and+PHY+IP\" target=\"_blank\" rel=\"nofollow noopener\">Design\u00adWa\u00adre\u00ae <span class=\"caps\">HBM3<\/span> Con\u00adtrol\u00adler and&nbsp;<span class=\"xn-person\"><span class=\"caps\">PHY<\/span> <span class=\"caps\">IP<\/span><\/span><\/a>, built on sili\u00adcon-pro\u00adven <span class=\"caps\">HBM2E<\/span> <span class=\"caps\">IP<\/span>, levera\u00adge Syn\u00adop\u00adsys\u2019 inter\u00adpo\u00adser exper\u00adti\u00adse to pro\u00advi\u00adde a low-risk solu\u00adti\u00adon that enables high memo\u00adry band\u00adwidth at up to 921 <span class=\"caps\">GB<\/span>\/s.<br>\n (\u2026) <a class=\"moretag\" href=\"https:\/\/www.planet3dnow.de\/cms\/63606-synopsys-accelerates-multi-die-designs-with-industrys-first-complete-hbm3-ip-and-verification-solutions\/\">Wei\u00adter\u00adle\u00adsen&nbsp;\u00bb<\/a><\/p>\n","protected":false},"author":593,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[2621,2275],"class_list":["post-63606","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","tag-hbm3","tag-synopsys","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/63606","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/593"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=63606"}],"version-history":[{"count":1,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/63606\/revisions"}],"predecessor-version":[{"id":63607,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/63606\/revisions\/63607"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=63606"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=63606"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=63606"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}