{"id":63894,"date":"2021-11-09T06:38:49","date_gmt":"2021-11-09T05:38:49","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=63894"},"modified":"2021-11-09T06:38:49","modified_gmt":"2021-11-09T05:38:49","slug":"amd-unveils-workload-tailored-innovations-and-products-at-the-accelerated-data-center-premiere","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/63894-amd-unveils-workload-tailored-innovations-and-products-at-the-accelerated-data-center-premiere\/","title":{"rendered":"<span class=\"caps\">AMD<\/span> Unveils Workload-Tailored Innovations and Products at The Accelerated Data Center Premiere"},"content":{"rendered":"<p>\u2014 <span class=\"caps\">AMD<\/span> laun\u00adches <span class=\"caps\">AMD<\/span> Instinct\u2122 <span class=\"caps\">MI200<\/span> series acce\u00adle\u00adra\u00adtors, pre\u00adviews 3rd&nbsp;Gen <span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span>\u2122 pro\u00adces\u00adsors with <span class=\"caps\">AMD<\/span> <span class=\"caps\">3D<\/span> V\u2011Cache, and pro\u00advi\u00addes new details on expan\u00added set of next-gene\u00adra\u00adti\u00adon <span class=\"caps\">EPYC<\/span>\u2122 pro\u00adces\u00adsors powered by \u201cZen 4\u201d and \u201cZen 4c\u201d <span class=\"caps\">CPU<\/span>&nbsp;cores\u2014<\/p>\n<p>\u2014 Meta choo\u00adses <span class=\"caps\">EPYC<\/span>\u2122 CPUs for its data center&nbsp;\u2014<\/p>\n<p><span class=\"caps\">SANTA<\/span> <span class=\"caps\">CLARA<\/span>, Calif., Nov. 08, 2021 (<span class=\"caps\">GLOBE<\/span> <span class=\"caps\">NEWSWIRE<\/span>) \u2014 <span class=\"caps\">AMD<\/span> (<span class=\"caps\">NASDAQ<\/span>: <span class=\"caps\">AMD<\/span>) held the vir\u00adtu\u00adal&nbsp;Acce\u00adle\u00adra\u00adted Data Cen\u00adter Pre\u00admie\u00adre, laun\u00adching the new <span class=\"caps\">AMD<\/span> Instinct\u2122 <span class=\"caps\">MI200<\/span> series acce\u00adle\u00adra\u00adtors, the world\u2019s fas\u00adtest acce\u00adle\u00adra\u00adtor for high per\u00adfor\u00admance com\u00adpu\u00adting (<span class=\"caps\">HPC<\/span>) and arti\u00adfi\u00adci\u00adal intel\u00adli\u00adgence (<span class=\"caps\">AI<\/span>) workload\u00adsi, and pro\u00advi\u00added a pre\u00adview of the inno\u00adva\u00adti\u00adve 3rd&nbsp;Gen <span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span>\u2122 pro\u00adces\u00adsors with <span class=\"caps\">AMD<\/span> <span class=\"caps\">3D<\/span> V\u2011Cache. <span class=\"caps\">AMD<\/span> also reve\u00ada\u00adled new infor\u00adma\u00adti\u00adon about its next gene\u00adra\u00adti\u00adon \u201cZen 4\u201d pro\u00adces\u00adsor core and announ\u00adced the new \u201cZen 4c\u201d pro\u00adces\u00adsor core, both of which will power future <span class=\"caps\">AMD<\/span> ser\u00adver pro\u00adces\u00adsors and are desi\u00adgned to extend the company\u2019s lea\u00adder\u00adship pro\u00adducts for the data center.<\/p>\n<p><span class=\"dquo\">\u201c<\/span>We are in a high-per\u00adfor\u00admance com\u00adpu\u00adting mega\u00adcy\u00adcle that is dri\u00adving demand for more com\u00adpu\u00adte to power the ser\u00advices and devices that impact every aspect of our dai\u00adly lives,\u201d said Dr. Lisa Su, pre\u00adsi\u00addent and <span class=\"caps\">CEO<\/span>, <span class=\"caps\">AMD<\/span>. \u201cWe are buil\u00adding signi\u00adfi\u00adcant momen\u00adtum in the data cen\u00adter with our lea\u00adder\u00adship pro\u00adduct port\u00adfo\u00adlio, inclu\u00adding Meta\u2019s adop\u00adti\u00adon of <span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span> to power their infra\u00adstruc\u00adtu\u00adre and the buil\u00addout of Fron\u00adtier, the first U.S. exas\u00adca\u00adle super\u00adcom\u00adpu\u00adter which will be powered by <span class=\"caps\">EPYC<\/span> and <span class=\"caps\">AMD<\/span> Instinct pro\u00adces\u00adsors. In addi\u00adti\u00adon, today we announ\u00adced a breadth of new pro\u00adducts that build on that momen\u00adtum in next-gene\u00adra\u00adti\u00adon <span class=\"caps\">EPYC<\/span> pro\u00adces\u00adsors with new inno\u00adva\u00adtions in design, lea\u00adder\u00adship, <span class=\"caps\">3D<\/span> pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgy, and 5 nm high-per\u00adfor\u00admance manu\u00adfac\u00adtu\u00adring to fur\u00adther extend our lea\u00adder\u00adship for cloud, enter\u00adpri\u00adse and <span class=\"caps\">HPC<\/span> customers.\u201d<\/p>\n<p><strong>Meta Adopts <span class=\"caps\">EPYC<\/span> CPUs [03:09 \u2013 05:29]<\/strong><br>\n<span class=\"caps\">AMD<\/span> announ\u00adced Meta&nbsp;is the latest major hypers\u00adca\u00adle cloud com\u00adpa\u00adny that has adopted <span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span> CPUs to power its data cen\u00adters. <span class=\"caps\">AMD<\/span> and Meta work\u00aded tog\u00ade\u00adther to defi\u00adne an open, cloud-sca\u00adle, sin\u00adgle-socket ser\u00adver desi\u00adgned for per\u00adfor\u00admance and power effi\u00adci\u00aden\u00adcy, based on the 3rd&nbsp;Gen <span class=\"caps\">EPYC<\/span> pro\u00adces\u00adsor. Fur\u00adther details will be dis\u00adcus\u00adsed at the Open Com\u00adpu\u00adte Glo\u00adbal Sum\u00admit later this&nbsp;week.&nbsp;<\/p>\n<p><strong>Advan\u00adced Pack\u00ada\u00adging Dri\u00adving Data Cen\u00adter Per\u00adfor\u00admance [05:35 \u2013 18:00]<\/strong><br>\n<span class=\"caps\">AMD<\/span> pre\u00adview\u00aded the use of inno\u00adva\u00adti\u00adve <span class=\"caps\">3D<\/span> chip\u00adlet pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgy in the data cen\u00adter with the first ser\u00adver <span class=\"caps\">CPU<\/span> using high-per\u00adfor\u00admance <span class=\"caps\">3D<\/span> die stack\u00ading. The 3rd&nbsp;Gen <span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span> pro\u00adces\u00adsors with <span class=\"caps\">AMD<\/span> <span class=\"caps\">3D<\/span> V\u2011Cache, code\u00adna\u00admed \u201cMilan\u2011X,\u201d repres\u00adents an inno\u00adva\u00adti\u00adve step for\u00adward in <span class=\"caps\">CPU<\/span> design and pack\u00ada\u00adging, and will offer a 50% avera\u00adge per\u00adfor\u00admance uplift across tar\u00adge\u00adted tech\u00adni\u00adcal com\u00adpu\u00adting workloadsii.<\/p>\n<p>3rd&nbsp;Gen <span class=\"caps\">EPYC<\/span> with <span class=\"caps\">AMD<\/span> <span class=\"caps\">3D<\/span> V\u2011Cache will offer the same capa\u00adbi\u00adli\u00adties and fea\u00adtures as the 3rd&nbsp;Gen <span class=\"caps\">EPYC<\/span> pro\u00adces\u00adsors and they will be drop-in com\u00adpa\u00adti\u00adble with a <span class=\"caps\">BIOS<\/span> upgrade, deli\u00adve\u00adring easy adop\u00adti\u00adon and per\u00adfor\u00admance enhancements.<br>\nMicro\u00adsoft Azu\u00adre <span class=\"caps\">HPC<\/span> vir\u00adtu\u00adal machi\u00adnes fea\u00adturing 3rd&nbsp;Gen <span class=\"caps\">EPYC<\/span> with <span class=\"caps\">AMD<\/span> <span class=\"caps\">3D<\/span> V\u2011Cache are available today in Pri\u00adva\u00adte Pre\u00adview, with broad roll\u00adout in the coming weeks. More infor\u00adma\u00adti\u00adon on per\u00adfor\u00admance and avai\u00adla\u00adbi\u00adli\u00adty is available&nbsp;here.<br>\n3rd&nbsp;Gen <span class=\"caps\">EPYC<\/span> CPUs with <span class=\"caps\">AMD<\/span> <span class=\"caps\">3D<\/span> V\u2011Cache will launch in <span class=\"caps\">Q1<\/span> 2022. Part\u00adners inclu\u00adding Cis\u00adco, Dell Tech\u00adno\u00adlo\u00adgies, Leno\u00advo, <span class=\"caps\">HPE<\/span> and Super\u00admi\u00adcro are plan\u00adning to offer ser\u00adver solu\u00adti\u00adons with the\u00adse processors.<\/p>\n<p><strong>Deli\u00adve\u00adring Exas\u00adca\u00adle Class Per\u00adfor\u00admance for Acce\u00adle\u00adra\u00adted Com\u00adpu\u00adting [18:02 \u2013 31:50]<\/strong><br>\n<span class=\"caps\">AMD<\/span>&nbsp;laun\u00adched the <span class=\"caps\">AMD<\/span> Instinct <span class=\"caps\">MI200<\/span> series acce\u00adle\u00adra\u00adtors. Based on the <span class=\"caps\">AMD<\/span> <span class=\"caps\">CDNA<\/span>\u2122 2 archi\u00adtec\u00adtu\u00adre, the <span class=\"caps\">MI200<\/span> series acce\u00adle\u00adra\u00adtors are the most advan\u00adced acce\u00adle\u00adra\u00adtors in the worl\u00addiii&nbsp;and pro\u00advi\u00adde up to 4.9x hig\u00adher peak per\u00adfor\u00admance for <span class=\"caps\">HPC<\/span> workload\u00adsiv&nbsp;and 1.<span class=\"caps\">2X<\/span> hig\u00adher peak flops of mixed pre\u00adcis\u00adi\u00adon per\u00adfor\u00admance for lea\u00adder\u00adship <span class=\"caps\">AI<\/span> trai\u00adning, hel\u00adping to fuel the con\u00adver\u00adgence of <span class=\"caps\">HPC<\/span> and&nbsp;<span class=\"caps\">AI<\/span>.<\/p>\n<p>Uti\u00adli\u00adzed in the Fron\u00adtier super\u00adcom\u00adpu\u00adter at&nbsp;Oak Ridge Natio\u00adnal Labo\u00adra\u00adto\u00adry, the <span class=\"caps\">HPC<\/span> and <span class=\"caps\">AI<\/span> per\u00adfor\u00admance capa\u00adbi\u00adli\u00adties in <span class=\"caps\">AMD<\/span> Instinct <span class=\"caps\">MI200<\/span> series acce\u00adle\u00adra\u00adtors will be key in enab\u00adling rese\u00adar\u00adchers and sci\u00aden\u00adtists to acce\u00adle\u00adra\u00adte their time to sci\u00adence and discovery.<\/p>\n<p><strong><span class=\"dquo\">\u201c<\/span>Zen 4\u201d Powered Data Cen\u00adter, Desi\u00adgned for Lea\u00adder\u00adship Per\u00adfor\u00admance [31:52 \u2013 36:22]<\/strong><br>\n<span class=\"caps\">AMD<\/span> pro\u00advi\u00added new details on the expan\u00added next gene\u00adra\u00adti\u00adon <span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span> pro\u00adces\u00adsors code\u00adna\u00admed \u201cGen\u00adoa\u201d and \u201cBer\u00adga\u00admo.\u201d<\/p>\n<p><span class=\"dquo\">\u201c<\/span>Gen\u00adoa\u201d is expec\u00adted to be the world\u2019s hig\u00adhest per\u00adfor\u00admance pro\u00adces\u00adsor for gene\u00adral pur\u00adpo\u00adse com\u00adpu\u00adting. It will have up to 96 high-per\u00adfor\u00admance \u201cZen 4\u201d cores pro\u00addu\u00adced on opti\u00admi\u00adzed 5nm tech\u00adno\u00adlo\u00adgy, and will sup\u00adport the next gene\u00adra\u00adti\u00adon of memo\u00adry and I\/O tech\u00adno\u00adlo\u00adgies with <span class=\"caps\">DDR5<\/span> and PCIe\u00ae 5. \u201cGen\u00adoa\u201d will also include sup\u00adport for <span class=\"caps\">CXL<\/span>, enab\u00adling signi\u00adfi\u00adcant memo\u00adry expan\u00adsi\u00adon capa\u00adbi\u00adli\u00adties for data cen\u00adter appli\u00adca\u00adti\u00adons. \u201cGen\u00adoa\u201d is on track for pro\u00adduc\u00adtion and launch in&nbsp;2022.<br>\n\u201cBer\u00adga\u00admo\u201d is a high-core count <span class=\"caps\">CPU<\/span>, tail\u00ador made for cloud nati\u00adve appli\u00adca\u00adti\u00adons, fea\u00adturing 128 high per\u00adfor\u00admance \u201cZen 4c\u201d cores. <span class=\"caps\">AMD<\/span> opti\u00admi\u00adzed the new \u201cZen 4c\u201d core for cloud-nati\u00adve com\u00adpu\u00adting, tuning the core design for den\u00adsi\u00adty and increased power effi\u00adci\u00aden\u00adcy to enable hig\u00adher core count pro\u00adces\u00adsors with breakth\u00adrough per\u00adfor\u00admance per-socket. \u201cBer\u00adga\u00admo\u201d comes with all the same soft\u00adware and secu\u00adri\u00adty fea\u00adtures and is socket com\u00adpa\u00adti\u00adble with \u201cGen\u00adoa.\u201d \u201cBer\u00adga\u00admo\u201d is on track to ship in the first half of&nbsp;2023.<\/p>\n<p>You can watch the&nbsp;full video here&nbsp;and learn more about all of the pro\u00adducts dis\u00adcus\u00adsed&nbsp;during the event&nbsp;here.<\/p>\n<p><strong>Sup\u00adport\u00ading Resources<\/strong><\/p>\n<ul>\n<li>Learn more about the<a href=\"https:\/\/www.amd.com\/en\/graphics\/instinct-server-accelerators\" target=\"_blank\" rel=\"nofollow noopener\">&nbsp;<span class=\"caps\">AMD<\/span> Instinct\u2122 accelerators<\/a><\/li>\n<li>Learn more about&nbsp;<a href=\"https:\/\/www.amd.com\/en\/processors\/epyc-server-cpu-family\" target=\"_blank\" rel=\"nofollow noopener\"><span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span>\u2122 processors&nbsp;<\/a><\/li>\n<li>Learn more about the&nbsp;<a href=\"https:\/\/www.olcf.ornl.gov\/frontier\/\" target=\"_blank\" rel=\"nofollow noopener\">Oak Ridge Natio\u00adnal Laboratory\u2019s Fron\u00adtier supercomputer<\/a><\/li>\n<li>Beco\u00adme a fan of <span class=\"caps\">AMD<\/span> on&nbsp;<a href=\"http:\/\/www.facebook.com\/AMD\" target=\"_blank\" rel=\"nofollow noopener\">Face\u00adbook<\/a><\/li>\n<li>Fol\u00adlow&nbsp;<span class=\"caps\">AMD<\/span>&nbsp;on&nbsp;<a href=\"https:\/\/twitter.com\/AMD\" target=\"_blank\" rel=\"nofollow noopener\">Twit\u00adter<\/a><\/li>\n<li>Con\u00adnect with <span class=\"caps\">AMD<\/span> On&nbsp;<a href=\"https:\/\/www.linkedin.com\/company\/amd\/\" target=\"_blank\" rel=\"nofollow noopener\">Lin\u00adke\u00addIn<\/a><\/li>\n<\/ul>\n<p><strong>About <span class=\"caps\">AMD<\/span><\/strong><br>\nFor more than 50 years <span class=\"caps\">AMD<\/span> has dri\u00adven inno\u00adva\u00adti\u00adon in high-per\u00adfor\u00admance com\u00adpu\u00adting, gra\u00adphics and visua\u00adliza\u00adti\u00adon tech\u00adno\u00adlo\u00adgies \u2015 the buil\u00adding blocks for gam\u00ading, immersi\u00adve plat\u00adforms and the dat\u00ada\u00adcen\u00adter. Hundreds of mil\u00adli\u00adons of con\u00adsu\u00admers, lea\u00adding For\u00adtu\u00adne 500 busi\u00adnesses and cut\u00adting-edge sci\u00aden\u00adti\u00adfic rese\u00adarch faci\u00adli\u00adties around the world rely on <span class=\"caps\">AMD<\/span> tech\u00adno\u00adlo\u00adgy dai\u00adly to impro\u00adve how they live, work and play. <span class=\"caps\">AMD<\/span> employees around the world are focu\u00adsed on buil\u00adding gre\u00adat pro\u00adducts that push the boun\u00adda\u00adries of what is pos\u00adsi\u00adble. For more infor\u00adma\u00adti\u00adon about how <span class=\"caps\">AMD<\/span> is enab\u00adling today and inspi\u00adring tomor\u00adrow, visit the <span class=\"caps\">AMD<\/span> (<span class=\"caps\">NASDAQ<\/span>: <span class=\"caps\">AMD<\/span>) &nbsp;web\u00adsite,&nbsp;blog,&nbsp;Face\u00adbook,&nbsp;Lin\u00adke\u00addIn&nbsp;and&nbsp;Twit\u00adter&nbsp;pages.&nbsp;<\/p>\n<p><span class=\"caps\">AMD<\/span>, the <span class=\"caps\">AMD<\/span> Arrow logo, <span class=\"caps\">EPYC<\/span>, <span class=\"caps\">AMD<\/span> Instinct, Infi\u00adni\u00adty Fabric and com\u00adbi\u00adna\u00adti\u00adons the\u00adreof are trade\u00admarks of Advan\u00adced Micro Devices, Inc. PCIe is a regis\u00adtered trade\u00admark of <span class=\"caps\">PCI-SIG<\/span> Cor\u00adpo\u00adra\u00adti\u00adon. Other names are for infor\u00adma\u00adtio\u00adnal pur\u00adpo\u00adses only and may be trade\u00admarks of their respec\u00adti\u00adve owners.<\/p>\n<p>This press release con\u00adta\u00adins for\u00adward-loo\u00adking state\u00adments con\u00adcer\u00adning Advan\u00adced Micro Devices, Inc. (<span class=\"caps\">AMD<\/span>) such as the fea\u00adtures, func\u00adtion\u00ada\u00adli\u00adty, per\u00adfor\u00admance, avai\u00adla\u00adbi\u00adli\u00adty, timing and expec\u00adted bene\u00adfits of <span class=\"caps\">AMD<\/span> pro\u00adducts inclu\u00adding the 3rd Gen <span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span>\u2122 pro\u00adces\u00adsors with <span class=\"caps\">AMD<\/span> <span class=\"caps\">3D<\/span> V\u2011Cache and <span class=\"caps\">AMD<\/span> Instinct\u2122 <span class=\"caps\">MI200<\/span> series acce\u00adle\u00adra\u00adtors as well as the \u201cZen 4\u201d data cen\u00adter road\u00admap, which are made pur\u00adsu\u00adant to the Safe Har\u00adbor pro\u00advi\u00adsi\u00adons of the Pri\u00adva\u00adte Secu\u00adri\u00adties Liti\u00adga\u00adti\u00adon Reform Act of 1995. For\u00adward-loo\u00adking state\u00adments are com\u00admon\u00adly iden\u00adti\u00adfied by words such as \u201cwould,\u201d \u201cmay,\u201d \u201cexpects,\u201d \u201cbelie\u00adves,\u201d \u201cplans,\u201d \u201cintends,\u201d \u201cpro\u00adjects\u201d and other terms with simi\u00adlar mea\u00adning. Inves\u00adtors are cau\u00adtio\u00adned that the for\u00adward-loo\u00adking state\u00adments in this press release are based on cur\u00adrent beliefs, assump\u00adti\u00adons and expec\u00adta\u00adti\u00adons, speak only as of the date of this press release and invol\u00adve risks and uncer\u00adtain\u00adties that could cau\u00adse actu\u00adal results to dif\u00adfer mate\u00adri\u00adal\u00adly from cur\u00adrent expec\u00adta\u00adti\u00adons. Such state\u00adments are sub\u00adject to cer\u00adtain known and unknown risks and uncer\u00adtain\u00adties, many of which are dif\u00adfi\u00adcult to pre\u00addict and gene\u00adral\u00adly bey\u00adond <span class=\"caps\">AMD<\/span>\u2019s con\u00adtrol, that could cau\u00adse actu\u00adal results and other future events to dif\u00adfer mate\u00adri\u00adal\u00adly from tho\u00adse expres\u00adsed in, or impli\u00aded or pro\u00adjec\u00adted by, the for\u00adward-loo\u00adking infor\u00adma\u00adti\u00adon and state\u00adments. Mate\u00adri\u00adal fac\u00adtors that could cau\u00adse actu\u00adal results to dif\u00adfer mate\u00adri\u00adal\u00adly from cur\u00adrent expec\u00adta\u00adti\u00adons include, wit\u00adhout limi\u00adta\u00adti\u00adon, the fol\u00adlo\u00adwing: Intel Corporation\u2019s domi\u00adnan\u00adce of the micro\u00adpro\u00adces\u00adsor mar\u00adket and its aggres\u00adsi\u00adve busi\u00adness prac\u00adti\u00adces; glo\u00adbal eco\u00adno\u00admic uncer\u00adtain\u00adty; loss of a signi\u00adfi\u00adcant cus\u00adto\u00admer; impact of the <span class=\"caps\">COVID-19<\/span> pan\u00adde\u00admic on <span class=\"caps\">AMD<\/span>\u2019s busi\u00adness, finan\u00adcial con\u00addi\u00adti\u00adon and results of ope\u00adra\u00adti\u00adons; com\u00adpe\u00adti\u00adti\u00adve mar\u00adkets in which <span class=\"caps\">AMD<\/span>\u2019s pro\u00adducts are sold; mar\u00adket con\u00addi\u00adti\u00adons of the indus\u00adtries in which <span class=\"caps\">AMD<\/span> pro\u00adducts are sold; cycli\u00adcal natu\u00adre of the semi\u00adcon\u00adduc\u00adtor indus\u00adtry; quar\u00adter\u00adly and sea\u00adso\u00adnal sales pat\u00adterns; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to ade\u00adqua\u00adte\u00adly pro\u00adtect its tech\u00adno\u00adlo\u00adgy or other intellec\u00adtu\u00adal pro\u00adper\u00adty; unfa\u00advorable cur\u00adren\u00adcy exch\u00adan\u00adge rate fluc\u00adtua\u00adtions; abili\u00adty of third par\u00adty manu\u00adfac\u00adtu\u00adr\u00aders to manu\u00adfac\u00adtu\u00adre <span class=\"caps\">AMD<\/span>\u2019s pro\u00adducts on a time\u00adly basis in suf\u00adfi\u00adci\u00adent quan\u00adti\u00adties and using com\u00adpe\u00adti\u00adti\u00adve tech\u00adno\u00adlo\u00adgies; avai\u00adla\u00adbi\u00adli\u00adty of essen\u00adti\u00adal equip\u00adment, mate\u00adri\u00adals, sub\u00adstra\u00adtes or manu\u00adfac\u00adtu\u00adring pro\u00adces\u00adses; abili\u00adty to achie\u00adve expec\u00adted manu\u00adfac\u00adtu\u00adring yields for <span class=\"caps\">AMD<\/span>\u2019s pro\u00adducts; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to intro\u00addu\u00adce pro\u00adducts on a time\u00adly basis with expec\u00adted fea\u00adtures and per\u00adfor\u00admance levels; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to gene\u00adra\u00adte reve\u00adnue from its semi-cus\u00adtom SoC pro\u00adducts; poten\u00adti\u00adal secu\u00adri\u00adty vul\u00adnerabi\u00adli\u00adties; poten\u00adti\u00adal secu\u00adri\u00adty inci\u00addents inclu\u00adding <span class=\"caps\">IT<\/span> outa\u00adges, data loss, data brea\u00adches and cyber-attacks; uncer\u00adtain\u00adties invol\u00adving the orde\u00adring and ship\u00adment of <span class=\"caps\">AMD<\/span>\u2019s pro\u00adducts; <span class=\"caps\">AMD<\/span>\u2019s reli\u00adance on third-par\u00adty intellec\u00adtu\u00adal pro\u00adper\u00adty to design and intro\u00addu\u00adce new pro\u00adducts in a time\u00adly man\u00adner; <span class=\"caps\">AMD<\/span>\u2019s reli\u00adance on third-par\u00adty com\u00adpa\u00adnies for design, manu\u00adfac\u00adtu\u00adre and sup\u00adp\u00adly of mother\u00adboards, soft\u00adware and other com\u00adpu\u00adter plat\u00adform com\u00adpon\u00adents; <span class=\"caps\">AMD<\/span>\u2019s reli\u00adance on Micro\u00adsoft and other soft\u00adware ven\u00addors\u2019 sup\u00adport to design and deve\u00adlop soft\u00adware to run on <span class=\"caps\">AMD<\/span>\u2019s pro\u00adducts; <span class=\"caps\">AMD<\/span>\u2019s reli\u00adance on third-par\u00adty dis\u00adtri\u00adbu\u00adtors and add-in-board part\u00adners; impact of modi\u00adfi\u00adca\u00adti\u00adon or inter\u00adrup\u00adti\u00adon of <span class=\"caps\">AMD<\/span>\u2019s inter\u00adnal busi\u00adness pro\u00adces\u00adses and infor\u00adma\u00adti\u00adon sys\u00adtems; com\u00adpa\u00adti\u00adbi\u00adli\u00adty of <span class=\"caps\">AMD<\/span>\u2019s pro\u00adducts with some or all indus\u00adtry-stan\u00addard soft\u00adware and hard\u00adware; cos\u00adts rela\u00adted to defec\u00adti\u00adve pro\u00adducts; effi\u00adci\u00aden\u00adcy of <span class=\"caps\">AMD<\/span>\u2019s sup\u00adp\u00adly chain; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to rely on third par\u00adty sup\u00adp\u00adly-chain logi\u00adstics func\u00adtions; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to effec\u00adtively con\u00adtrol sales of its pro\u00adducts on the gray mar\u00adket; impact of govern\u00adment actions and regu\u00adla\u00adti\u00adons such as export admi\u00adnis\u00adtra\u00adti\u00adon regu\u00adla\u00adti\u00adons, tariffs and trade pro\u00adtec\u00adtion mea\u00adsu\u00adres; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to rea\u00adli\u00adze its defer\u00adred tax assets; poten\u00adti\u00adal tax lia\u00adbi\u00adli\u00adties; cur\u00adrent and future claims and liti\u00adga\u00adti\u00adon; impact of envi\u00adron\u00admen\u00adtal laws, con\u00adflict mine\u00adrals-rela\u00adted pro\u00advi\u00adsi\u00adons and other laws or regu\u00adla\u00adti\u00adons; impact of acqui\u00adsi\u00adti\u00adons, joint ven\u00adtures and\/or invest\u00adments on <span class=\"caps\">AMD<\/span>\u2019s busi\u00adness, inclu\u00adding the announ\u00adced acqui\u00adsi\u00adti\u00adon of Xilinx, and abili\u00adty to inte\u00adgra\u00adte acqui\u00adred busi\u00adnesses; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to com\u00adple\u00adte the Xilinx mer\u00adger; impact of the announce\u00adment and pen\u00adden\u00adcy of the Xilinx mer\u00adger on <span class=\"caps\">AMD<\/span>\u2019s busi\u00adness; impact of any impair\u00adment of the com\u00adbi\u00adned company\u2019s assets on the com\u00adbi\u00adned company\u2019s finan\u00adcial posi\u00adti\u00adon and results of ope\u00adra\u00adti\u00adon; rest\u00adric\u00adtions impo\u00adsed by agree\u00adments gover\u00adning <span class=\"caps\">AMD<\/span>\u2019s notes and the revol\u00adving cre\u00addit faci\u00adli\u00adty; <span class=\"caps\">AMD<\/span>\u2019s indeb\u00adted\u00adness; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to gene\u00adra\u00adte suf\u00adfi\u00adci\u00adent cash to meet its working capi\u00adtal requi\u00adre\u00adments or gene\u00adra\u00adte suf\u00adfi\u00adci\u00adent reve\u00adnue and ope\u00adra\u00adting cash flow to make all of its plan\u00adned R<span class=\"amp\">&amp;<\/span>D or stra\u00adte\u00adgic invest\u00adments; poli\u00adti\u00adcal, legal, eco\u00adno\u00admic risks and natu\u00adral dis\u00adas\u00adters; future impairm\u00adents of good\u00adwill and tech\u00adno\u00adlo\u00adgy licen\u00adse purcha\u00adses; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to attract and retain qua\u00adli\u00adfied per\u00adson\u00adnel; <span class=\"caps\">AMD<\/span>\u2019s stock pri\u00adce vola\u00adti\u00adli\u00adty; and world\u00adwi\u00adde poli\u00adti\u00adcal con\u00addi\u00adti\u00adons. Inves\u00adtors are urged to review in detail the risks and uncer\u00adtain\u00adties in <span class=\"caps\">AMD<\/span>\u2019s Secu\u00adri\u00adties and Exch\u00adan\u00adge Com\u00admis\u00adsi\u00adon filings, inclu\u00adding but not limi\u00adt\u00aded to <span class=\"caps\">AMD<\/span>\u2019s most recent reports on Forms 10\u2011K and 10\u2011Q.<\/p>\n<p>i&nbsp;<span class=\"caps\">MI200-01<\/span>: World\u2019s fas\u00adtest data cen\u00adter <span class=\"caps\">GPU<\/span> is the <span class=\"caps\">AMD<\/span> Instinct\u2122 <span class=\"caps\">MI250X<\/span>. Cal\u00adcu\u00adla\u00adti\u00adons con\u00adduc\u00adted by <span class=\"caps\">AMD<\/span> Per\u00adfor\u00admance Labs as of Sep 15, 2021, for the <span class=\"caps\">AMD<\/span> Instinct\u2122 <span class=\"caps\">MI250X<\/span> (<span class=\"caps\">128GB<\/span> HBM2e <span class=\"caps\">OAM<\/span> modu\u00adle) acce\u00adle\u00adra\u00adtor at 1,700 MHz peak boost engi\u00adne clock resul\u00adted in 95.7 <span class=\"caps\">TFLOPS<\/span> peak theo\u00adre\u00adti\u00adcal dou\u00adble pre\u00adcis\u00adi\u00adon (<span class=\"caps\">FP64<\/span> Matrix), 47.9 <span class=\"caps\">TFLOPS<\/span> peak theo\u00adre\u00adti\u00adcal dou\u00adble pre\u00adcis\u00adi\u00adon (<span class=\"caps\">FP64<\/span>), 95.7 <span class=\"caps\">TFLOPS<\/span> peak theo\u00adre\u00adti\u00adcal sin\u00adgle pre\u00adcis\u00adi\u00adon matrix (<span class=\"caps\">FP32<\/span> Matrix), 47.9 <span class=\"caps\">TFLOPS<\/span> peak theo\u00adre\u00adti\u00adcal sin\u00adgle pre\u00adcis\u00adi\u00adon (<span class=\"caps\">FP32<\/span>), 383.0 <span class=\"caps\">TFLOPS<\/span> peak theo\u00adre\u00adti\u00adcal half pre\u00adcis\u00adi\u00adon (<span class=\"caps\">FP16<\/span>), and 383.0 <span class=\"caps\">TFLOPS<\/span> peak theo\u00adre\u00adti\u00adcal Bfloat16 for\u00admat pre\u00adcis\u00adi\u00adon (<span class=\"caps\">BF16<\/span>) floa\u00adting-point per\u00adfor\u00admance. Cal\u00adcu\u00adla\u00adti\u00adons con\u00adduc\u00adted by <span class=\"caps\">AMD<\/span> Per\u00adfor\u00admance Labs as of Sep 18, 2020 for the <span class=\"caps\">AMD<\/span> Instinct\u2122 <span class=\"caps\">MI100<\/span> (<span class=\"caps\">32GB<\/span> <span class=\"caps\">HBM2<\/span> PCIe\u00ae card) acce\u00adle\u00adra\u00adtor at 1,502 MHz peak boost engi\u00adne clock resul\u00adted in 11.54 <span class=\"caps\">TFLOPS<\/span> peak theo\u00adre\u00adti\u00adcal dou\u00adble pre\u00adcis\u00adi\u00adon (<span class=\"caps\">FP64<\/span>), 46.1 <span class=\"caps\">TFLOPS<\/span> peak theo\u00adre\u00adti\u00adcal sin\u00adgle pre\u00adcis\u00adi\u00adon matrix (<span class=\"caps\">FP32<\/span>), 23.1 <span class=\"caps\">TFLOPS<\/span> peak theo\u00adre\u00adti\u00adcal sin\u00adgle pre\u00adcis\u00adi\u00adon (<span class=\"caps\">FP32<\/span>), 184.6 <span class=\"caps\">TFLOPS<\/span> peak theo\u00adre\u00adti\u00adcal half pre\u00adcis\u00adi\u00adon (<span class=\"caps\">FP16<\/span>) floa\u00adting-point per\u00adfor\u00admance. Published results on the NVi\u00addia Ampere <span class=\"caps\">A100<\/span> (<span class=\"caps\">80GB<\/span>) <span class=\"caps\">GPU<\/span> acce\u00adle\u00adra\u00adtor, boost engi\u00adne clock of 1410 MHz, resul\u00adted in 19.5 <span class=\"caps\">TFLOPS<\/span> peak dou\u00adble pre\u00adcis\u00adi\u00adon ten\u00adsor cores (<span class=\"caps\">FP64<\/span> Ten\u00adsor Core), 9.7 <span class=\"caps\">TFLOPS<\/span> peak dou\u00adble pre\u00adcis\u00adi\u00adon (<span class=\"caps\">FP64<\/span>). 19.5 <span class=\"caps\">TFLOPS<\/span> peak sin\u00adgle pre\u00adcis\u00adi\u00adon (<span class=\"caps\">FP32<\/span>), 78 <span class=\"caps\">TFLOPS<\/span> peak half pre\u00adcis\u00adi\u00adon (<span class=\"caps\">FP16<\/span>), 312 <span class=\"caps\">TFLOPS<\/span> peak half pre\u00adcis\u00adi\u00adon (<span class=\"caps\">FP16<\/span> Ten\u00adsor Flow), 39 <span class=\"caps\">TFLOPS<\/span> peak Bfloat 16 (<span class=\"caps\">BF16<\/span>), 312 <span class=\"caps\">TFLOPS<\/span> peak Bfloat16 for\u00admat pre\u00adcis\u00adi\u00adon (<span class=\"caps\">BF16<\/span> Ten\u00adsor Flow), theo\u00adre\u00adti\u00adcal floa\u00adting-point per\u00adfor\u00admance. The <span class=\"caps\">TF32<\/span> data for\u00admat is not <span class=\"caps\">IEEE<\/span> com\u00adpli\u00adant and not included in this com\u00adpa\u00adri\u00adson. https:\/\/www.nvidia.com\/content\/dam\/en-zz\/Solutions\/Data-Center\/nvidia-ampere-architecture-whitepaper.pdf, page 15, Table&nbsp;1.<br>\nii&nbsp;<span class=\"caps\">MLNX-021R<\/span>: <span class=\"caps\">AMD<\/span> inter\u00adnal test\u00ading as of 09\/27\/2021 on 2x <span class=\"caps\">64C<\/span> 3rd Gen <span class=\"caps\">EPYC<\/span> with <span class=\"caps\">AMD<\/span> <span class=\"caps\">3D<\/span> V\u2011Cache (Milan\u2011X) com\u00adpared to 2x <span class=\"caps\">64C<\/span> <span class=\"caps\">AMD<\/span> 3rd Gen <span class=\"caps\">EPYC<\/span> 7763 CPUs using cumu\u00adla\u00adti\u00adve avera\u00adge of each of the fol\u00adlo\u00adwing benchmark\u2019s maxi\u00admum test result score: <span class=\"caps\">ANSYS<\/span>\u00ae Flu\u00adent\u00ae 2021.1, <span class=\"caps\">ANSYS<\/span>\u00ae <span class=\"caps\">CFX<\/span>\u00ae 2021.<span class=\"caps\">R2<\/span>, and Alta\u00adir Radioss 2021. Results may&nbsp;vary.<br>\niii&nbsp;<span class=\"caps\">MI200-31<\/span>: As of Octo\u00adber 20th, 2021, the <span class=\"caps\">AMD<\/span> Instinct\u2122 <span class=\"caps\">MI200<\/span> series acce\u00adle\u00adra\u00adtors are the \u201cMost advan\u00adced ser\u00adver acce\u00adle\u00adra\u00adtors (GPUs) for data cen\u00adter,\u201d defi\u00adned as the only ser\u00adver acce\u00adle\u00adra\u00adtors to use the advan\u00adced 6nm manu\u00adfac\u00adtu\u00adring tech\u00adno\u00adlo\u00adgy on a ser\u00adver. <span class=\"caps\">AMD<\/span> on 6nm for <span class=\"caps\">AMD<\/span> Instinct <span class=\"caps\">MI200<\/span> series ser\u00adver acce\u00adle\u00adra\u00adtors. Nvi\u00addia on 7nm for Nvi\u00addia Ampere <span class=\"caps\">A100<\/span> <span class=\"caps\">GPU<\/span>. https:\/\/developer.nvidia.com\/blog\/nvidia-ampere-architecture-in-depth\/<br>\niv&nbsp;<span class=\"caps\">MI200-02<\/span>: Cal\u00adcu\u00adla\u00adti\u00adons con\u00adduc\u00adted by <span class=\"caps\">AMD<\/span> Per\u00adfor\u00admance Labs as of Sep 15, 2021, for the <span class=\"caps\">AMD<\/span> Instinct\u2122 <span class=\"caps\">MI250X<\/span> acce\u00adle\u00adra\u00adtor (<span class=\"caps\">128GB<\/span> HBM2e <span class=\"caps\">OAM<\/span> modu\u00adle) at 1,700 MHz peak boost engi\u00adne clock resul\u00adted in 95.7 <span class=\"caps\">TFLOPS<\/span> peak dou\u00adble pre\u00adcis\u00adi\u00adon matrix (<span class=\"caps\">FP64<\/span> Matrix) theo\u00adre\u00adti\u00adcal, floa\u00adting-point per\u00adfor\u00admance. Published results on the NVi\u00addia Ampere <span class=\"caps\">A100<\/span> (<span class=\"caps\">80GB<\/span>) <span class=\"caps\">GPU<\/span> acce\u00adle\u00adra\u00adtor resul\u00adted in 19.5 <span class=\"caps\">TFLOPS<\/span> peak dou\u00adble pre\u00adcis\u00adi\u00adon (<span class=\"caps\">FP64<\/span> Ten\u00adsor Core) theo\u00adre\u00adti\u00adcal, floa\u00adting-point per\u00adfor\u00admance. Results found at: https:\/\/www.nvidia.com\/content\/dam\/en-zz\/Solutions\/Data-Center\/nvidia-ampere-architecture-whitepaper.pdf, page 15, Table&nbsp;1.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>\u2014 <span class=\"caps\">AMD<\/span> laun\u00adches <span class=\"caps\">AMD<\/span> Instinct\u2122 <span class=\"caps\">MI200<\/span> series acce\u00adle\u00adra\u00adtors, pre\u00adviews 3rd&nbsp;Gen <span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span>\u2122 pro\u00adces\u00adsors with <span class=\"caps\">AMD<\/span> <span class=\"caps\">3D<\/span> V\u2011Cache, and pro\u00advi\u00addes new details on expan\u00added set of next-gene\u00adra\u00adti\u00adon <span class=\"caps\">EPYC<\/span>\u2122 pro\u00adces\u00adsors powered by \u201cZen 4\u201d and \u201cZen 4c\u201d <span class=\"caps\">CPU<\/span>&nbsp;cores\u2014<\/p>\n<p>\u2014 Meta choo\u00adses <span class=\"caps\">EPYC<\/span>\u2122 CPUs for its data center&nbsp;\u2014<\/p>\n<p><span class=\"caps\">SANTA<\/span> <span class=\"caps\">CLARA<\/span>, Calif., Nov. 08, 2021 (<span class=\"caps\">GLOBE<\/span> <span class=\"caps\">NEWSWIRE<\/span>) \u2014 <span class=\"caps\">AMD<\/span> (<span class=\"caps\">NASDAQ<\/span>: <span class=\"caps\">AMD<\/span>) held the vir\u00adtu\u00adal&nbsp;Acce\u00adle\u00adra\u00adted Data Cen\u00adter Pre\u00admie\u00adre, laun\u00adching the new <span class=\"caps\">AMD<\/span> Instinct\u2122 <span class=\"caps\">MI200<\/span> series acce\u00adle\u00adra\u00adtors, the world\u2019s fas\u00adtest acce\u00adle\u00adra\u00adtor for high per\u00adfor\u00admance com\u00adpu\u00adting (<span class=\"caps\">HPC<\/span>) and arti\u00adfi\u00adci\u00adal intel\u00adli\u00adgence (<span class=\"caps\">AI<\/span>) workload\u00adsi, and pro\u00advi\u00added a pre\u00adview of the inno\u00adva\u00adti\u00adve 3rd&nbsp;Gen <span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span>\u2122 pro\u00adces\u00adsors with <span class=\"caps\">AMD<\/span> <span class=\"caps\">3D<\/span> V\u2011Cache. <span class=\"caps\">AMD<\/span> also reve\u00ada\u00adled new infor\u00adma\u00adti\u00adon about its next gene\u00adra\u00adti\u00adon \u201cZen 4\u201d pro\u00adces\u00adsor core and announ\u00adced the new \u201cZen 4c\u201d pro\u00adces\u00adsor core, both of which will power future <span class=\"caps\">AMD<\/span> ser\u00adver pro\u00adces\u00adsors and are desi\u00adgned to extend the company\u2019s lea\u00adder\u00adship pro\u00adducts for the data center.<\/p>\n<p><span class=\"dquo\">\u201c<\/span>We are in a high-per\u00adfor\u00admance com\u00adpu\u00adting mega\u00adcy\u00adcle that is dri\u00adving demand for more com\u00adpu\u00adte to power the ser\u00advices and devices that impact every aspect of our dai\u00adly lives,\u201d said Dr. Lisa Su, pre\u00adsi\u00addent and <span class=\"caps\">CEO<\/span>, <span class=\"caps\">AMD<\/span>. \u201cWe are buil\u00adding signi\u00adfi\u00adcant momen\u00adtum in the data cen\u00adter with our lea\u00adder\u00adship pro\u00adduct port\u00adfo\u00adlio, inclu\u00adding Meta\u2019s adop\u00adti\u00adon of <span class=\"caps\">AMD<\/span> <span class=\"caps\">EPYC<\/span> to power their infra\u00adstruc\u00adtu\u00adre and the buil\u00addout of Fron\u00adtier, the first U.S. exas\u00adca\u00adle super\u00adcom\u00adpu\u00adter which will be powered by <span class=\"caps\">EPYC<\/span> and <span class=\"caps\">AMD<\/span> Instinct pro\u00adces\u00adsors. In addi\u00adti\u00adon, today we announ\u00adced a breadth of new pro\u00adducts that build on that momen\u00adtum in next-gene\u00adra\u00adti\u00adon <span class=\"caps\">EPYC<\/span> pro\u00adces\u00adsors with new inno\u00adva\u00adtions in design, lea\u00adder\u00adship, <span class=\"caps\">3D<\/span> pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgy, and 5 nm high-per\u00adfor\u00admance manu\u00adfac\u00adtu\u00adring to fur\u00adther extend our lea\u00adder\u00adship for cloud, enter\u00adpri\u00adse and <span class=\"caps\">HPC<\/span> cus\u00adto\u00admers.\u201d (\u2026) <a class=\"moretag\" href=\"https:\/\/www.planet3dnow.de\/cms\/63894-amd-unveils-workload-tailored-innovations-and-products-at-the-accelerated-data-center-premiere\/\">Wei\u00adter\u00adle\u00adsen&nbsp;\u00bb<\/a><\/p>\n","protected":false},"author":593,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[966,1307,1209,2643],"class_list":["post-63894","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","tag-amd","tag-epyc","tag-instinct","tag-meta","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/63894","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/593"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=63894"}],"version-history":[{"count":2,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/63894\/revisions"}],"predecessor-version":[{"id":63896,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/63894\/revisions\/63896"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=63894"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=63894"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=63894"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}