{"id":64033,"date":"2021-11-15T17:52:51","date_gmt":"2021-11-15T16:52:51","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=64033"},"modified":"2021-11-15T17:52:51","modified_gmt":"2021-11-15T16:52:51","slug":"xilinx-launches-alveo-u55c-its-most-powerful-accelerator-card-ever-purpose-built-for-hpc-and-big-data-workloads","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/64033-xilinx-launches-alveo-u55c-its-most-powerful-accelerator-card-ever-purpose-built-for-hpc-and-big-data-workloads\/","title":{"rendered":"Xilinx Launches Alveo U55C<\/span>, Its Most Powerful Accelerator Card Ever, Purpose-Built for HPC<\/span> and Big Data Workloads"},"content":{"rendered":"

Breakthrough HPC<\/span> clustering solution and simplified programmability enable massive scale-out of cutting-edge compute across existing customer infrastructure and network<\/i><\/h3>\n

ST<\/span>. LOUIS<\/span>\u2013(BUSINESS<\/span> WIRE<\/span><\/a>)\u2013SC21<\/span> <\/b>\u2013<\/b> <\/b>Xilinx, Inc. (NASDAQ<\/span>: XLNX<\/span>), the lea\u00adder in adap\u00adti\u00adve com\u00adpu\u00adting, today at the SC21<\/span><\/a> super\u00adcom\u00adpu\u00adting con\u00adfe\u00adrence intro\u00addu\u00adced the Alveo\u2122 U55C<\/span><\/a> data cen\u00adter acce\u00adle\u00adra\u00adtor card and a new stan\u00addards-based, API-dri\u00adven clus\u00adte\u00adring solu\u00adti\u00adon for deploy\u00ading FPGAs at mas\u00adsi\u00adve sca\u00adle. The Alveo U55C<\/span> acce\u00adle\u00adra\u00adtor brings supe\u00adri\u00ador per\u00adfor\u00admance-per-watt to high per\u00adfor\u00admance com\u00adpu\u00adting (HPC<\/span>) and data\u00adba\u00adse workloads and easi\u00adly sca\u00adles through the Xilinx\u00ae<\/sup> HPC<\/span> clus\u00adte\u00adring solution.<\/p>\n

Pur\u00adpo\u00adse-built for HPC<\/span> and big data workloads, the new Alveo U55C<\/span> card is the company\u2019s most powerful Alveo<\/a> acce\u00adle\u00adra\u00adtor card ever, offe\u00adring the hig\u00adhest com\u00adpu\u00adte den\u00adsi\u00adty and HBM<\/span> capa\u00adci\u00adty in the Alveo acce\u00adle\u00adra\u00adtor port\u00adfo\u00adlio. Tog\u00ade\u00adther with the new Xilinx RoCE v2-based clus\u00adte\u00adring solu\u00adti\u00adon, a broad spec\u00adtrum of cus\u00adto\u00admers with lar\u00adge-sca\u00adle com\u00adpu\u00adte workloads can now imple\u00adment powerful FPGA-based HPC<\/span> clus\u00adte\u00adring using their exis\u00adting data cen\u00adter infra\u00adstruc\u00adtu\u00adre and network.<\/p>\n

\u201c<\/span>Sca\u00adling out Alveo com\u00adpu\u00adte capa\u00adbi\u00adli\u00adties to tar\u00adget HPC<\/span> workloads is now easier, more effi\u00adci\u00adent and more powerful than ever,\u201d said Salil Raje, exe\u00adcu\u00adti\u00adve vice pre\u00adsi\u00addent and gene\u00adral mana\u00adger, Data Cen\u00adter Group at Xilinx. \u201cArchi\u00adtec\u00adtu\u00adral\u00adly, FPGA-based acce\u00adle\u00adra\u00adtors like Alveo cards pro\u00advi\u00adde the hig\u00adhest per\u00adfor\u00admance at the lowest cost for many com\u00adpu\u00adte-inten\u00adsi\u00adve workloads. By intro\u00addu\u00adcing a stan\u00addards-based metho\u00addo\u00adlo\u00adgy that enables the crea\u00adti\u00adon of Alveo HPC<\/span> clus\u00adters using a customer\u2019s exis\u00adting infra\u00adstruc\u00adtu\u00adre and net\u00adwork, we\u2019re deli\u00adve\u00adring tho\u00adse key advan\u00adta\u00adges at mas\u00adsi\u00adve sca\u00adle to any data cen\u00adter. This is a major leap for\u00adward for even broa\u00adder adop\u00adti\u00adon of Alveo and adap\u00adti\u00adve com\u00adpu\u00adting throug\u00adhout the data center.\u201d<\/p>\n

Built for HPC<\/span> and big data applications<\/b><\/p>\n

The Alveo U55C<\/span> card com\u00adbi\u00adnes many key fea\u00adtures that today\u2019s HPC<\/span> workloads requi\u00adre. It deli\u00advers more par\u00adal\u00adle\u00adlism of data pipe\u00adlines, supe\u00adri\u00ador memo\u00adry manage\u00adment, opti\u00admi\u00adzed data move\u00adment throug\u00adhout the pipe\u00adline, and the hig\u00adhest per\u00adfor\u00admance-per-watt in the Alveo port\u00adfo\u00adlio. The Alveo U55C<\/span> card is a sin\u00adgle-slot full height, half length (FHHL<\/span>) form fac\u00adtor with a low 150W<\/span> max power. It offers supe\u00adri\u00ador com\u00adpu\u00adte den\u00adsi\u00adty and dou\u00adbles the HBM2<\/span> to 16GB<\/span> com\u00adpared to its pre\u00adde\u00adces\u00adsor, the dual-slot Alveo U280<\/span><\/a> card. The U55C<\/span> pro\u00advi\u00addes more com\u00adpu\u00adte in a smal\u00adler form fac\u00adtor for crea\u00adting den\u00adse Alveo acce\u00adle\u00adra\u00adtor-based clus\u00adters. It\u2019s built for high-den\u00adsi\u00adty strea\u00adming data, high IO<\/span> math, and big com\u00adpu\u00adte pro\u00adblems that requi\u00adre sca\u00adle-out like big data ana\u00adly\u00adtics and AI<\/span> applications.<\/p>\n

Lever\u00adaging RoCE v2 and data cen\u00adter bridging, cou\u00adpled with 200 Gbps band\u00adwidth, the API-dri\u00adven clus\u00adte\u00adring solu\u00adti\u00adon enables an Alveo net\u00adwork that com\u00adpe\u00adtes with Infi\u00adni\u00adBand net\u00adworks in per\u00adfor\u00admance and laten\u00adcy, with no ven\u00addor lock-in. MPI<\/span> inte\u00adgra\u00adti\u00adon allows for HPC<\/span> deve\u00adlo\u00adpers to sca\u00adle out Alveo data pipe\u00adlining from the Xilinx Vitis\u2122 uni\u00adfied soft\u00adware plat\u00adform<\/a>. Uti\u00adli\u00adzing exis\u00adting open stan\u00addards and frame\u00adworks, it\u2019s now pos\u00adsi\u00adble to sca\u00adle out across hundreds of Alveo cards regard\u00adless of the ser\u00adver plat\u00adforms and net\u00adwork infra\u00adstruc\u00adtu\u00adre and with shared workloads and memory.<\/p>\n

Soft\u00adware deve\u00adlo\u00adpers and data sci\u00aden\u00adtists can unlock the bene\u00adfits of Alveo and adap\u00adti\u00adve com\u00adpu\u00adting through high-level pro\u00adgramma\u00adbi\u00adli\u00adty of both the appli\u00adca\u00adti\u00adon and clus\u00adter uti\u00adli\u00adzing the Vitis platform\u200b. Xilinx has inves\u00adted hea\u00advi\u00adly in the Vitis deve\u00adlo\u00adp\u00adment plat\u00adform and tools flow to make adap\u00adti\u00adve com\u00adpu\u00adting more acces\u00adsi\u00adble to soft\u00adware deve\u00adlo\u00adpers and data sci\u00aden\u00adtists wit\u00adhout hard\u00adware exper\u00adti\u00adse. The major AI<\/span> frame\u00adworks like Pytorch and Ten\u00adsor\u00adflow are sup\u00adport\u00aded, as well as high-level pro\u00adgramming lan\u00adguages like C, C++ and Python, allo\u00adwing deve\u00adlo\u00adpers to build domain solu\u00adti\u00adons using spe\u00adci\u00adfic APIs and libra\u00adri\u00ades, or uti\u00adli\u00adze Xilinx soft\u00adware deve\u00adlo\u00adp\u00adment kits, to easi\u00adly acce\u00adle\u00adra\u00adte key HPC<\/span> workloads within an exis\u00adting data center.<\/p>\n

HPC<\/span> cus\u00adto\u00admer use cases<\/b><\/p>\n

CSIRO<\/span><\/a>, Australia\u2019s natio\u00adnal rese\u00adarch orga\u00adniza\u00adti\u00adon along with the world\u2019s lar\u00adgest radio astro\u00adno\u00admy anten\u00adna array, is uti\u00adli\u00adzing Alveo U55C<\/span> cards for signal pro\u00adces\u00adsing in the Squa\u00adre Kilo\u00adme\u00adter Array radio telescope. Deploy\u00ading the Alveo cards as net\u00adwork-atta\u00adched acce\u00adle\u00adra\u00adtors with HBM<\/span> allows for mas\u00adsi\u00adve through\u00adput at sca\u00adle across the HPC<\/span> signal pro\u00adces\u00adsing clus\u00adter. The Alveo acce\u00adle\u00adra\u00adtor-based clus\u00adter allows CSIRO<\/span> to tack\u00adle the mas\u00adsi\u00adve com\u00adpu\u00adte task of aggre\u00adga\u00adting, fil\u00adte\u00adring, pre\u00adpa\u00adring and pro\u00adces\u00adsing data from 131,000 anten\u00adnas in real time. The 460Gbps of HBM2<\/span> band\u00adwidth across the signal pro\u00adces\u00adsing clus\u00adter is ser\u00adved by 420 Alveo U55C<\/span> cards ful\u00adly net\u00adwork\u00aded tog\u00ade\u00adther across P4-enab\u00adled 100Gbps swit\u00adches. The Alveo U55C<\/span> clus\u00adter deli\u00advers pro\u00adces\u00adsing per\u00adfor\u00admance with over\u00adall through\u00adput at 15Tb\/s in a com\u00adpact power and cost effi\u00adci\u00adent foot\u00adprint. CSIRO<\/span> is now com\u00adple\u00adting an exam\u00adp\u00adle Alveo refe\u00adrence design in order to help other radio astro\u00adno\u00admy or adja\u00adcent indus\u00adtries achie\u00adve the same success.<\/p>\n

Ansys LS-DYNA<\/span><\/a> crash simu\u00adla\u00adti\u00adon soft\u00adware is used by near\u00adly every auto\u00admo\u00adti\u00adve com\u00adpa\u00adny in the world. The design of safe\u00adty and struc\u00adtu\u00adral sys\u00adtems hin\u00adges on the per\u00adfor\u00admance of models as they miti\u00adga\u00adte the cos\u00adts of phy\u00adsi\u00adcal crash test\u00ading with com\u00adpu\u00adter-aided design fini\u00adte ele\u00adment method (FEM<\/span>) simu\u00adla\u00adti\u00adons. FEM<\/span> sol\u00advers are the pri\u00adma\u00adry algo\u00adrith\u00adms dri\u00adving simu\u00adla\u00adti\u00adons with hundreds of mil\u00adli\u00adons of degrees of free\u00addom, the\u00adse enorm\u00adous algo\u00adrith\u00adms can be bro\u00adken out into more rudi\u00admen\u00adta\u00adry sol\u00advers like PCG<\/span>, spar\u00adse matri\u00adces and ICCG<\/span>. By sca\u00adling out across many Alveo cards with hyper\u00adpar\u00adal\u00adlel data pipe\u00adlining, LS-DYNA<\/span> can acce\u00adle\u00adra\u00adte per\u00adfor\u00admance by more than 5X<\/span> in com\u00adpa\u00adri\u00adson to x86 CPUs. This results in more work per clock cycle in an Alveo pipe\u00adline with LS-DYNA<\/span> cus\u00adto\u00admers bene\u00adfiting from game chan\u00adging simu\u00adla\u00adti\u00adon times.<\/p>\n

\u201c<\/span>In the spi\u00adrit of relent\u00adless inno\u00adva\u00adti\u00adon, we\u2019re exci\u00adted about col\u00adla\u00adbo\u00adra\u00adting with Xilinx to signi\u00adfi\u00adcant\u00adly acce\u00adle\u00adra\u00adte the fini\u00adte-ele\u00adment sol\u00advers, which can repre\u00adsent 90% of the com\u00adpu\u00adte workload for impli\u00adcit mecha\u00adnics, in our LS-DYNA<\/span> simu\u00adla\u00adti\u00adon appli\u00adca\u00adti\u00adon,\u201d said Wim Slag\u00adter, stra\u00adte\u00adgic part\u00adner\u00adships direc\u00adtor at Ansys. \u201cWe look for\u00adward to Xilinx acce\u00adle\u00adra\u00adti\u00adon hel\u00adping us in our mis\u00adsi\u00adon to sup\u00adport inno\u00adva\u00adtors in engi\u00adnee\u00adring what\u2019s ahead.\u201d<\/p>\n

Tiger\u00adGraph<\/a>, pro\u00advi\u00adder of a lea\u00adding graph ana\u00adly\u00adtics plat\u00adform, is using mul\u00adti\u00adple Alveo U55C<\/span> cards to clus\u00adter and acce\u00adle\u00adra\u00adte the two most pro\u00adli\u00adfic algo\u00adrith\u00adms that dri\u00adve graph-based recom\u00admen\u00adda\u00adti\u00adon and clus\u00adte\u00adring engi\u00adnes. Graph data\u00adba\u00adses are a dis\u00adrup\u00adti\u00adve plat\u00adform for data sci\u00aden\u00adtists. Graphs take data from silos and bring focus to the rela\u00adti\u00adonships bet\u00adween data. The next fron\u00adtier for graph is fin\u00adding tho\u00adse ans\u00adwers in real time. Alveo U55C<\/span> acce\u00adle\u00adra\u00adtes the query times and pre\u00addic\u00adtions for recom\u00admen\u00adda\u00adti\u00adon engi\u00adnes from minu\u00adtes down to mil\u00adli\u00adse\u00adconds. By uti\u00adli\u00adzing mul\u00adti\u00adple U55C<\/span> cards to sca\u00adle up ana\u00adly\u00adtics, the supe\u00adri\u00ador com\u00adpu\u00adta\u00adtio\u00adnal power and memo\u00adry band\u00adwidth acce\u00adle\u00adra\u00adtes graph query speeds up to 45X<\/span> fas\u00adter com\u00adpared to CPU-based clus\u00adters. The qua\u00adli\u00adty of scores also increa\u00adses by up to 35%, resul\u00adting in grea\u00adter con\u00adfi\u00addence dra\u00adma\u00adti\u00adcal\u00adly lowe\u00adring fal\u00adse posi\u00adti\u00adves to low sin\u00adgle digits.<\/p>\n

Pro\u00adduct avai\u00adla\u00adbi\u00adli\u00adty and easy evaluations<\/b><\/p>\n

The Alveo U55C<\/span> card is curr\u00adent\u00adly available on Xilinx.com and through Xilinx aut\u00adho\u00adri\u00adzed dis\u00adtri\u00adbu\u00adtors. It\u2019s also available for easy eva\u00adlua\u00adti\u00adon via public cloud-based FPGA-as-a-Ser\u00advice pro\u00advi\u00adders, as well as sel\u00adect colo\u00adca\u00adti\u00adon data cen\u00adters for pri\u00adva\u00adte pre\u00adviews. Clus\u00adte\u00adring is available now for pri\u00adva\u00adte pre\u00adviews, with gene\u00adral avai\u00adla\u00adbi\u00adli\u00adty expec\u00adted in the second quar\u00adter of next year.<\/p>\n

Xilinx is show\u00adca\u00adsing the Alveo U55C<\/span> acce\u00adle\u00adra\u00adtor card, along with part\u00adner solu\u00adti\u00adons, at the SC21<\/span> con\u00adfe\u00adrence taking place this week. Regis\u00adter at SC21<\/span><\/a> to visit the Xilinx vir\u00adtu\u00adal booth.<\/p>\n

Fol\u00adlow Xilinx on Twit\u00adter<\/a>, Lin\u00adke\u00addIn<\/a> and Face\u00adbook<\/a>.<\/p>\n

About Xilinx<\/b><\/p>\n

Xilinx, Inc. deve\u00adlo\u00adps high\u00adly fle\u00adxi\u00adble and adap\u00adti\u00adve pro\u00adces\u00adsing plat\u00adforms that enable rapid inno\u00adva\u00adti\u00adon across a varie\u00adty of tech\u00adno\u00adlo\u00adgies \u2014 from the cloud, to the edge, to the end\u00adpoint. Xilinx is the inven\u00adtor of the FPGA<\/span> and Adap\u00adti\u00adve SoCs (inclu\u00adding our Adap\u00adti\u00adve Com\u00adpu\u00adte Acce\u00adle\u00adra\u00adti\u00adon Plat\u00adform, or ACAP<\/span>), desi\u00adgned to deli\u00adver the most dyna\u00admic com\u00adpu\u00adting tech\u00adno\u00adlo\u00adgy in the indus\u00adtry. We col\u00adla\u00adbo\u00adra\u00adte with our cus\u00adto\u00admers to crea\u00adte sca\u00adlable, dif\u00adfe\u00adren\u00adtia\u00adted and intel\u00adli\u00adgent solu\u00adti\u00adons that enable the adap\u00adta\u00adble, intel\u00adli\u00adgent and con\u00adnec\u00adted world of the future. For more infor\u00adma\u00adti\u00adon, visit xilinx.com.<\/p>\n","protected":false},"excerpt":{"rendered":"

<\/p>

Breakthrough HPC<\/span> clustering solution and simplified programmability enable massive scale-out of cutting-edge compute across existing customer infrastructure and network<\/i><\/h3>\n

ST<\/span>. LOUIS<\/span>\u2013(BUSINESS<\/span> WIRE<\/span><\/a>)\u2013SC21<\/span> <\/b>\u2013<\/b> <\/b>Xilinx, Inc. (NASDAQ<\/span>: XLNX<\/span>), the lea\u00adder in adap\u00adti\u00adve com\u00adpu\u00adting, today at the SC21<\/span><\/a> super\u00adcom\u00adpu\u00adting con\u00adfe\u00adrence intro\u00addu\u00adced the Alveo\u2122 U55C<\/span><\/a> data cen\u00adter acce\u00adle\u00adra\u00adtor card and a new stan\u00addards-based, API-dri\u00adven clus\u00adte\u00adring solu\u00adti\u00adon for deploy\u00ading FPGAs at mas\u00adsi\u00adve sca\u00adle. The Alveo U55C<\/span> acce\u00adle\u00adra\u00adtor brings supe\u00adri\u00ador per\u00adfor\u00admance-per-watt to high per\u00adfor\u00admance com\u00adpu\u00adting (HPC<\/span>) and data\u00adba\u00adse workloads and easi\u00adly sca\u00adles through the Xilinx\u00ae<\/sup> HPC<\/span> clus\u00adte\u00adring solution.<\/p>\n

Pur\u00adpo\u00adse-built for HPC<\/span> and big data workloads, the new Alveo U55C<\/span> card is the company\u2019s most powerful Alveo<\/a> acce\u00adle\u00adra\u00adtor card ever, offe\u00adring the hig\u00adhest com\u00adpu\u00adte den\u00adsi\u00adty and HBM<\/span> capa\u00adci\u00adty in the Alveo acce\u00adle\u00adra\u00adtor port\u00adfo\u00adlio. Tog\u00ade\u00adther with the new Xilinx RoCE v2-based clus\u00adte\u00adring solu\u00adti\u00adon, a broad spec\u00adtrum of cus\u00adto\u00admers with lar\u00adge-sca\u00adle com\u00adpu\u00adte workloads can now imple\u00adment powerful FPGA-based HPC<\/span> clus\u00adte\u00adring using their exis\u00adting data cen\u00adter infra\u00adstruc\u00adtu\u00adre and net\u00adwork. (\u2026) Wei\u00adter\u00adle\u00adsen \u00bb<\/a><\/p>\n","protected":false},"author":593,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[2658,540,1583],"class_list":["post-64033","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","tag-alveo-u55c","tag-hpc","tag-xilinx","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/64033","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/593"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=64033"}],"version-history":[{"count":1,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/64033\/revisions"}],"predecessor-version":[{"id":64034,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/64033\/revisions\/64034"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=64033"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=64033"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=64033"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}