{"id":64786,"date":"2022-03-21T14:48:33","date_gmt":"2022-03-21T13:48:33","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=64786"},"modified":"2022-03-21T14:48:33","modified_gmt":"2022-03-21T13:48:33","slug":"3rd-gen-amd-epyc-processors-with-amd-3d-v-cache-technology-deliver-outstanding-leadership-performance-in-technical-computing-workloads","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/64786-3rd-gen-amd-epyc-processors-with-amd-3d-v-cache-technology-deliver-outstanding-leadership-performance-in-technical-computing-workloads\/","title":{"rendered":"3rd Gen AMD<\/span> EPYC<\/span> Processors with AMD<\/span> 3D<\/span> V\u2011Cache Technology Deliver Outstanding Leadership Performance in Technical Computing Workloads"},"content":{"rendered":"

\u2014 Newest addi\u00adti\u00adon to 3rd<\/em><\/sup> Gen AMD<\/span> EPYC<\/span><\/em>\u2122 fami\u00adly fea\u00adtures 768MB<\/span> of L3<\/span> cache, drop-in plat\u00adform com\u00adpa\u00adti\u00adbi\u00adli\u00adty, and modern secu\u00adri\u00adty features \u2014<\/em><\/p>\n

\u2014 The EPYC<\/span> pro\u00adces\u00adsor eco\u00adsys\u00adtem for tech\u00adni\u00adcal com\u00adpu\u00adting grows with solu\u00adti\u00adons from major OEMs, ODMs, SIs, ISVs and the cloud \u2014<\/p>\n

SANTA<\/span> CLARA<\/span>, Calif., March 21, 2022 (GLOBE<\/span> NEWSWIRE<\/span>) \u2014 AMD<\/span><\/a> (NASDAQ<\/span>: AMD<\/span>) announ\u00adced the gene\u00adral avai\u00adla\u00adbi\u00adli\u00adty of the world\u2019s first data cen\u00adter CPU<\/span> using 3D<\/span> die stack\u00ading, the 3<\/a>rd<\/sup><\/a> Gen AMD<\/span> EPYC<\/span>\u2122 pro\u00adces\u00adsors with AMD<\/span> 3D<\/span> V\u2011Cache\u2122 tech\u00adno\u00adlo\u00adgy<\/a>, form\u00ader\u00adly code\u00adna\u00admed \u201cMilan\u2011X.\u201d Built on the \u201cZen 3\u201d core archi\u00adtec\u00adtu\u00adre, the\u00adse pro\u00adces\u00adsors expand the 3<\/a>rd<\/sup><\/a> Gen EPYC<\/span> CPU<\/span> fami\u00adly<\/a> and can deli\u00adver up to 66 per\u00adcent per\u00adfor\u00admance uplift across a varie\u00adty of tar\u00adge\u00adted tech\u00adni\u00adcal com\u00adpu\u00adting workloads ver\u00adsus com\u00adpa\u00adra\u00adble, non-sta\u00adcked 3rd<\/sup> Gen AMD<\/span> EPYC<\/span> pro\u00adces\u00adsors.1<\/sup>,<\/sup> 2<\/em><\/sup><\/p>\n

The\u00adse new pro\u00adces\u00adsors fea\u00adture the industry\u2019s lar\u00adgest L3<\/span> cache,3<\/sup> deli\u00adve\u00adring the same socket, soft\u00adware com\u00adpa\u00adti\u00adbi\u00adli\u00adty and modern secu\u00adri\u00adty fea\u00adtures as 3rd<\/sup> Gen AMD<\/span> EPYC<\/span> CPUs while pro\u00advi\u00adding out\u00adstan\u00adding per\u00adfor\u00admance for tech\u00adni\u00adcal com\u00adpu\u00adting workloads such as com\u00adpu\u00adta\u00adtio\u00adnal flu\u00adid dyna\u00admics (CFD<\/span>), fini\u00adte ele\u00adment ana\u00adly\u00adsis (FEA<\/span>), elec\u00adtro\u00adnic design auto\u00adma\u00adti\u00adon (EDA<\/span>) and struc\u00adtu\u00adral ana\u00adly\u00adsis. The\u00adse workloads are cri\u00adti\u00adcal design tools for com\u00adpa\u00adnies that must model the com\u00adple\u00adxi\u00adties of the phy\u00adsi\u00adcal world to crea\u00adte simu\u00adla\u00adti\u00adons that test and vali\u00adda\u00adte engi\u00adnee\u00adring designs for some of the world\u2019s most inno\u00adva\u00adte products.<\/p>\n

\u201c<\/span>Buil\u00adding upon our momen\u00adtum in the data cen\u00adter as well as our histo\u00adry of indus\u00adtry-firsts, 3rd<\/sup> Gen AMD<\/span> EPYC<\/span> pro\u00adces\u00adsors with AMD<\/span> 3D<\/span> V\u2011Cache tech\u00adno\u00adlo\u00adgy show\u00adca\u00adse our lea\u00adder\u00adship design and pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgy enab\u00adling us to offer the industry\u2019s first workload-tail\u00ado\u00adred ser\u00adver pro\u00adces\u00adsor with 3D<\/span> die stack\u00ading tech\u00adno\u00adlo\u00adgy,\u201d said Dan McNa\u00adma\u00adra, seni\u00ador vice pre\u00adsi\u00addent and gene\u00adral mana\u00adger, Ser\u00adver Busi\u00adness Unit, AMD<\/span>. \u201cOur latest pro\u00adces\u00adsors with AMD<\/span> 3D<\/span> V\u2011Cache tech\u00adno\u00adlo\u00adgy pro\u00advi\u00adde breakth\u00adrough per\u00adfor\u00admance for mis\u00adsi\u00adon-cri\u00adti\u00adcal tech\u00adni\u00adcal com\u00adpu\u00adting workloads lea\u00adding to bet\u00adter desi\u00adgned pro\u00adducts and fas\u00adter time to market.\u201d<\/p>\n

\u201c<\/span>Cus\u00adto\u00admers\u2019 increased adop\u00adti\u00adon of data-rich appli\u00adca\u00adti\u00adons requi\u00adres a new approach to data cen\u00adter infra\u00adstruc\u00adtu\u00adre. Micron and AMD<\/span> share a visi\u00adon of deli\u00adve\u00adring full capa\u00adbi\u00adli\u00adty of lea\u00adding DDR5<\/span> memo\u00adry to high-per\u00adfor\u00admance data cen\u00adter plat\u00adforms,\u201d said Raj Haz\u00adra, seni\u00ador vice pre\u00adsi\u00addent and gene\u00adral mana\u00adger of the Com\u00adpu\u00adte and Net\u00adwor\u00adking Busi\u00adness Unit at Micron. \u201cOur deep col\u00adla\u00adbo\u00adra\u00adti\u00adon with AMD<\/span> includes rea\u00addy\u00ading AMD<\/span> plat\u00adforms for Micron\u2019s latest DDR5<\/span> solu\u00adti\u00adons as well as brin\u00adging 3rd<\/sup> Gen AMD<\/span> EPYC<\/span> pro\u00adces\u00adsors with AMD<\/span> 3D<\/span> V\u2011Cache tech\u00adno\u00adlo\u00adgy into our own data cen\u00adters, whe\u00adre we are alre\u00ada\u00addy see\u00ading up to a 40% per\u00adfor\u00admance impro\u00adve\u00adment over 3rd<\/sup> Gen AMD<\/span> EPYC<\/span> pro\u00adces\u00adsors wit\u00adhout AMD<\/span> 3D<\/span> V\u2011Cache on sel\u00adect EDA<\/span> workloads.\u201d<\/p>\n

Lea\u00adding Pack\u00ada\u00adging Innovations<\/strong>
\nCache size increa\u00adses have been at the fore\u00adfront of per\u00adfor\u00admance impro\u00adve\u00adment, par\u00adti\u00adcu\u00adlar\u00adly for tech\u00adni\u00adcal com\u00adpu\u00adting workloads rely\u00ading hea\u00advi\u00adly on lar\u00adge data sets. The\u00adse workloads bene\u00adfit from increased cache size, howe\u00adver 2D<\/span> chip designs have phy\u00adsi\u00adcal limi\u00adta\u00adti\u00adons on the amount of cache that can effec\u00adtively be built on the CPU<\/span>. AMD<\/span> 3D<\/span> V\u2011Cache tech\u00adno\u00adlo\u00adgy sol\u00adves the\u00adse phy\u00adsi\u00adcal chal\u00adlenges by bon\u00adding the AMD<\/span> \u201cZen 3\u201d core to the cache modu\u00adle, incre\u00adasing the amount of L3<\/span> while mini\u00admi\u00adzing laten\u00adcy and incre\u00adasing through\u00adput. This tech\u00adno\u00adlo\u00adgy repres\u00adents an inno\u00adva\u00adti\u00adve step for\u00adward in CPU<\/span> design and pack\u00ada\u00adging and enables breakth\u00adrough per\u00adfor\u00admance in tar\u00adge\u00adted tech\u00adni\u00adcal com\u00adpu\u00adting workloads.<\/p>\n

Breakth\u00adrough Performance<\/strong>
\nThe world\u2019s hig\u00adhest per\u00adfor\u00admance ser\u00adver pro\u00adces\u00adsors for tech\u00adni\u00adcal com\u00adpu\u00adting,4<\/sup> the 3rd<\/sup> Gen AMD<\/span> EPYC<\/span> pro\u00adces\u00adsors with AMD<\/span> 3D<\/span> V\u2011Cache tech\u00adno\u00adlo\u00adgy deli\u00adver fas\u00adter time-to-results on tar\u00adge\u00adted workloads, such as:<\/p>\n