{"id":67906,"date":"2023-04-21T06:42:38","date_gmt":"2023-04-21T04:42:38","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=67906"},"modified":"2023-04-21T06:42:38","modified_gmt":"2023-04-21T04:42:38","slug":"amd-bolsters-embedded-portfolio-with-new-ryzen-embedded-5000-series-processors-for-networking-solutions","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/67906-amd-bolsters-embedded-portfolio-with-new-ryzen-embedded-5000-series-processors-for-networking-solutions\/","title":{"rendered":"<span class=\"caps\">AMD<\/span> Bolsters Embedded Portfolio with New Ryzen Embedded 5000 Series Processors for Networking Solutions"},"content":{"rendered":"<p align=\"left\"><span class=\"caps\">SANTA<\/span> <span class=\"caps\">CLARA<\/span>, Calif., April 20, 2023 (<span class=\"caps\">GLOBE<\/span> <span class=\"caps\">NEWSWIRE<\/span>) \u2014&nbsp;<a title=\"AMD\" href=\"http:\/\/www.amd.com\/\" target=\"_blank\" rel=\"nofollow noopener\"><span class=\"caps\">AMD<\/span><\/a>&nbsp;(<span class=\"caps\">NASDAQ<\/span>: <span class=\"caps\">AMD<\/span>) today announ\u00adced the avai\u00adla\u00adbi\u00adli\u00adty of its high-per\u00adfor\u00admance <span class=\"caps\">AMD<\/span> Ryzen\u2122 Embedded 5000 Series, a new solu\u00adti\u00adon for cus\u00adto\u00admers requi\u00adring power-effi\u00adci\u00adent pro\u00adces\u00adsors opti\u00admi\u00adzed for \u201calways on\u201d net\u00adwor\u00adking fire\u00adwalls, net\u00adwork-atta\u00adched sto\u00adrage sys\u00adtems and other secu\u00adri\u00adty appli\u00adca\u00adti\u00adons. The Ryzen Embedded 5000 Series rounds out the \u201cZen 3\u201d-based <span class=\"caps\">AMD<\/span> embedded pro\u00adces\u00adsor port\u00adfo\u00adlio which also includes the Ryzen Embedded <span class=\"caps\">V3000<\/span> and <span class=\"caps\">EPYC<\/span>\u2122 Embedded 7000 series families.<\/p>\n<p>Built on 7nm tech\u00adno\u00adlo\u00adgy with plan\u00adned five-year manu\u00adfac\u00adtu\u00adring avai\u00adla\u00adbi\u00adli\u00adty, and equip\u00adped with 6, 8, 12 or 16 cores and 24 lanes of PCIe\u00ae Gen4 con\u00adnec\u00adti\u00advi\u00adty, Ryzen Embedded 5000 Series pro\u00adces\u00adsors are desi\u00adgned for enter\u00adpri\u00adse relia\u00adbi\u00adli\u00adty to sup\u00adport the con\u00adsis\u00adtent uptime requi\u00adre\u00adments nee\u00added by secu\u00adri\u00adty and net\u00adwor\u00adking cus\u00adto\u00admers. Ryzen Embedded 5000 Series pro\u00adces\u00adsors include robust relia\u00adbi\u00adli\u00adty, avai\u00adla\u00adbi\u00adli\u00adty and ser\u00advicea\u00adbi\u00adli\u00adty (<span class=\"caps\">RAS<\/span>) fea\u00adtures, inclu\u00adding an ECC-sup\u00adport\u00aded memo\u00adry sub\u00adsys\u00adtem. With a ther\u00admal design power (<span class=\"caps\">TDP<\/span>) pro\u00adfi\u00adle ran\u00adging from <span class=\"caps\">65W<\/span> to <span class=\"caps\">105W<\/span>, Ryzen Embedded 5000 pro\u00adces\u00adsors enable the reduc\u00adtion of over\u00adall sys\u00adtem coo\u00adling foot\u00adprint for space-cons\u00adtrai\u00adned and cost-sen\u00adsi\u00adti\u00adve applications.<\/p>\n<p><span class=\"dquo\">\u201c<\/span>Ryzen Embedded 5000 pro\u00adces\u00adsors deli\u00adver the ide\u00adal com\u00adbi\u00adna\u00adti\u00adon of per\u00adfor\u00admance and relia\u00adbi\u00adli\u00adty requi\u00adred for 24x7 secu\u00adri\u00adty and net\u00adwor\u00adking appli\u00adca\u00adti\u00adons,\u201d said Raj\u00adnee\u00adsh Gaur, cor\u00adpo\u00adra\u00adte vice pre\u00adsi\u00addent <span class=\"amp\">&amp;<\/span> gene\u00adral mana\u00adger, Embedded Solu\u00adti\u00adons Group, <span class=\"caps\">AMD<\/span>. \u201cThis expan\u00adsi\u00adon of our embedded pro\u00adduct port\u00adfo\u00adlio offers a mid-ran\u00adge solu\u00adti\u00adon that fills the gap bet\u00adween our low-power <span class=\"caps\">BGA<\/span> Ryzen Embedded and our world-class <span class=\"caps\">EPYC<\/span> embedded fami\u00adly for cus\u00adto\u00admers requi\u00adring both high per\u00adfor\u00admance and sca\u00adla\u00adbi\u00adli\u00adty of up to 16&nbsp;cores.\u201d<\/p>\n<p><span class=\"dquo\">\u201c<\/span><span class=\"caps\">AMD<\/span>\u2019s suc\u00adcess in the embedded mar\u00adket is built on offe\u00adring dif\u00adfe\u00adren\u00adtia\u00adted and sca\u00adlable offe\u00adrings that address a wide ran\u00adge of appli\u00adca\u00adti\u00adons with dif\u00adfe\u00adrent power, per\u00adfor\u00admance and envi\u00adron\u00admen\u00adtal&nbsp;requi\u00adre\u00adments,\u201d said Kevin Kre\u00adwell, prin\u00adci\u00adpal ana\u00adlyst at <span class=\"caps\">TIRIAS<\/span> Rese\u00adarch. \u201cThe <span class=\"caps\">AMD<\/span>&nbsp;Ryzen Embedded 5000 strikes an opti\u00admal balan\u00adce of power and per\u00adfor\u00admance for appli\u00adca\u00adti\u00adons ran\u00adging from small-form fac\u00adtor&nbsp;embedded sys\u00adtems to sto\u00adrage, secu\u00adri\u00adty, and net\u00adwor\u00adking sys\u00adtems, sui\u00adting the broa\u00addest ran\u00adge of cus\u00adto\u00admers and use&nbsp;cases.\u201d<\/p>\n<p><strong>Ryzen Embedded 5000 Series pro\u00adces\u00adsors&nbsp;offer:<\/strong><\/p>\n<ul>\n<li>Sca\u00adla\u00adbi\u00adli\u00adty up to 16 cores and 32 threads<\/li>\n<li>Up to <span class=\"caps\">64MB<\/span> of shared <span class=\"caps\">L3<\/span> <span class=\"caps\">CPU<\/span>&nbsp;Cache<\/li>\n<li>Ener\u00adgy effi\u00adci\u00adent <span class=\"caps\">TDP<\/span> from <span class=\"caps\">65W<\/span> to&nbsp;<span class=\"caps\">105W<\/span><\/li>\n<li>ECC-sup\u00adport\u00aded memo\u00adry and secu\u00adri\u00adty features<\/li>\n<li>24 lanes of PCIe\u00ae 4 con\u00adnec\u00adti\u00advi\u00adty (expan\u00adda\u00adble I\/O up to 36 lanes with <span class=\"caps\">AMD<\/span> <span class=\"caps\">X570<\/span> chipset)<\/li>\n<li>Opti\u00admi\u00adzed per\u00adfor\u00admance for enter\u00adpri\u00adse reliability<\/li>\n<\/ul>\n<p><strong>Ryzen Embedded 5000 Series Pro\u00adces\u00adsor Pro\u00adduct&nbsp;Chart<\/strong><\/p>\n<div class=\"table-responsive\">\n<table>\n<tbody>\n<tr>\n<td>Model<\/td>\n<td><span class=\"caps\">CPU<\/span> Cores<\/td>\n<td>Threads count<\/td>\n<td><span class=\"caps\">CPU<\/span> Base Freq (GHz)<\/td>\n<td><span class=\"caps\">CPU<\/span> <span class=\"caps\">1T<\/span> Boost Freq (up to&nbsp;GHz1)<\/td>\n<td><span class=\"caps\">L3<\/span> <span class=\"caps\">CPU<\/span> Cache (<span class=\"caps\">MB<\/span>)<\/td>\n<td>Nomi\u00adnal <span class=\"caps\">TDP<\/span> (W)<\/td>\n<td><span class=\"caps\">DDR4<\/span> Chan\u00adnels<\/td>\n<td>Max <span class=\"caps\">DDR4<\/span> rate (<span class=\"caps\">MT<\/span>\/s) (<span class=\"caps\">1DPC<\/span>)<\/td>\n<td>PCIe\u00ae Gen 43&nbsp;Lanes<\/td>\n<td>Socket<\/td>\n<\/tr>\n<tr>\n<td><span class=\"caps\">5950E<\/span><\/td>\n<td>16<\/td>\n<td>32<\/td>\n<td>3.05<\/td>\n<td>3.4<\/td>\n<td>64<\/td>\n<td>105<\/td>\n<td>2<\/td>\n<td>3200<\/td>\n<td>24<\/td>\n<td><span class=\"caps\">AM4<\/span><\/td>\n<\/tr>\n<tr>\n<td><span class=\"caps\">5900E<\/span><\/td>\n<td>12<\/td>\n<td>24<\/td>\n<td>3.35<\/td>\n<td>3.7<\/td>\n<td>64<\/td>\n<td>105<\/td>\n<td>2<\/td>\n<td>3200<\/td>\n<td>24<\/td>\n<td><span class=\"caps\">AM4<\/span><\/td>\n<\/tr>\n<tr>\n<td><span class=\"caps\">5800E<\/span><\/td>\n<td>8<\/td>\n<td>16<\/td>\n<td>3.4<\/td>\n<td>3.7<\/td>\n<td>32<\/td>\n<td>1002<\/td>\n<td>2<\/td>\n<td>3200<\/td>\n<td>24<\/td>\n<td><span class=\"caps\">AM4<\/span><\/td>\n<\/tr>\n<tr>\n<td><span class=\"caps\">5600E<\/span><\/td>\n<td>6<\/td>\n<td>12<\/td>\n<td>3.3<\/td>\n<td>3.6<\/td>\n<td>32<\/td>\n<td>65<\/td>\n<td>2<\/td>\n<td>3200<\/td>\n<td>24<\/td>\n<td><span class=\"caps\">AM4<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<p align=\"justify\"><sup>1<\/sup>Max boost for Ryzen Embedded 5000 pro\u00adces\u00adsors is the maxi\u00admum fre\u00adquen\u00adcy achie\u00adva\u00adble by any sin\u00adgle core on the pro\u00adces\u00adsor under nor\u00admal ope\u00adra\u00adting con\u00addi\u00adti\u00adons for enter\u00adpri\u00adse systems.<br>\n<sup>2<\/sup>Ryzen Embedded <span class=\"caps\">5800E<\/span> pro\u00adces\u00adsor sup\u00adports con\u00adfi\u00adgura\u00adble Ther\u00admal Design Power (cTDP) from <span class=\"caps\">65W<\/span> to&nbsp;<span class=\"caps\">100W<\/span>.<br>\n<sup>3<\/sup>Ryzen Embedded 5000 pro\u00adces\u00adsors sup\u00adport a total of 24 lanes of PCIe\u00ae Gen4. Optio\u00adnal\u00adly pai\u00adred with the <span class=\"caps\">AMD<\/span> <span class=\"caps\">X570<\/span> Chip\u00adset, up to 36 lanes of PCIe\u00ae Gen4 can be supported.<\/p>\n<p align=\"justify\"><span class=\"caps\">AMD<\/span> Ryzen Embedded 5000 Series pro\u00adces\u00adsors are curr\u00adent\u00adly in pro\u00adduc\u00adtion with five-year plan\u00adned manu\u00adfac\u00adtu\u00adring availability.<\/p>\n<p><strong>Sup\u00adport\u00ading Resources<\/strong><\/p>\n<ul>\n<li>Read more about the&nbsp;<a href=\"https:\/\/www.amd.com\/en\/technologies\/zen-core-3\" target=\"_blank\" rel=\"nofollow noopener\"><span class=\"caps\">AMD<\/span> \u201cZen 3\u201d Core Architecture<\/a><\/li>\n<li>Learn more about the&nbsp;<a title=\"AMD Ryzen Embedded Family\" href=\"https:\/\/www.amd.com\/en\/products\/embedded-ryzen-series\" target=\"_blank\" rel=\"nofollow noopener\"><span class=\"caps\">AMD<\/span> Ryzen Embedded Family<\/a><\/li>\n<li>Fol\u00adlow <span class=\"caps\">AMD<\/span> on&nbsp;<a title=\"Twitter\" href=\"https:\/\/twitter.com\/AMD\" target=\"_blank\" rel=\"nofollow noopener\">Twit\u00adter<\/a><\/li>\n<li>Con\u00adnect with <span class=\"caps\">AMD<\/span> on&nbsp;<a title=\"LinkedIn\" href=\"https:\/\/www.linkedin.com\/company\/amd\/\" target=\"_blank\" rel=\"nofollow noopener\">Lin\u00adke\u00addIn<\/a><\/li>\n<\/ul>\n<p><strong>About <span class=\"caps\">AMD<\/span><\/strong><br>\nFor more than 50 years <span class=\"caps\">AMD<\/span> has dri\u00adven inno\u00adva\u00adti\u00adon in high-per\u00adfor\u00admance com\u00adpu\u00adting, gra\u00adphics and visua\u00adliza\u00adti\u00adon tech\u00adno\u00adlo\u00adgies. Bil\u00adli\u00adons of peo\u00adp\u00adle, lea\u00adding For\u00adtu\u00adne 500 busi\u00adnesses and cut\u00adting-edge sci\u00aden\u00adti\u00adfic rese\u00adarch insti\u00adtu\u00adti\u00adons around the world rely on <span class=\"caps\">AMD<\/span> tech\u00adno\u00adlo\u00adgy dai\u00adly to impro\u00adve how they live, work and play. <span class=\"caps\">AMD<\/span> employees are focu\u00adsed on buil\u00adding lea\u00adder\u00adship high-per\u00adfor\u00admance and adap\u00adti\u00adve pro\u00adducts that push the boun\u00adda\u00adries of what is pos\u00adsi\u00adble. For more infor\u00adma\u00adti\u00adon about how <span class=\"caps\">AMD<\/span> is enab\u00adling today and inspi\u00adring tomor\u00adrow, visit the <span class=\"caps\">AMD<\/span> (<span class=\"caps\">NASDAQ<\/span>: <span class=\"caps\">AMD<\/span>)&nbsp;<a title=\"website\" href=\"http:\/\/www.amd.com\/\" target=\"_blank\" rel=\"nofollow noopener\">web\u00adsite<\/a>,&nbsp;<a title=\"blog\" href=\"https:\/\/community.amd.com\/\" target=\"_blank\" rel=\"nofollow noopener\">blog<\/a>,&nbsp;<a title=\"LinkedIn\" href=\"https:\/\/www.linkedin.com\/company\/amd\" target=\"_blank\" rel=\"nofollow noopener\">Lin\u00adke\u00addIn<\/a>&nbsp;and&nbsp;<a title=\"Twitter\" href=\"https:\/\/twitter.com\/amd\" target=\"_blank\" rel=\"nofollow noopener\">Twit\u00adter<\/a>&nbsp;pages.<\/p>\n<p><strong><span class=\"caps\">CAUTIONARY<\/span> <span class=\"caps\">STATEMENT<\/span><\/strong><\/p>\n<p>This press release con\u00adta\u00adins for\u00adward-loo\u00adking state\u00adments con\u00adcer\u00adning Advan\u00adced Micro Devices, Inc. (<span class=\"caps\">AMD<\/span>) inclu\u00adding the five-year plan\u00adned manu\u00adfac\u00adtu\u00adring avai\u00adla\u00adbi\u00adli\u00adty of the <span class=\"caps\">AMD<\/span> Ryzen<sup><span class=\"caps\">TM<\/span><\/sup>&nbsp;Embedded 5000 Series pro\u00adces\u00adsors, which are made pur\u00adsu\u00adant to the Safe Har\u00adbor pro\u00advi\u00adsi\u00adons of the Pri\u00adva\u00adte Secu\u00adri\u00adties Liti\u00adga\u00adti\u00adon Reform Act of 1995. For\u00adward-loo\u00adking state\u00adments are com\u00admon\u00adly iden\u00adti\u00adfied by words such as \u201cwould,\u201d \u201cmay,\u201d \u201cexpects,\u201d \u201cbelie\u00adves,\u201d \u201cplans,\u201d \u201cintends,\u201d \u201cpro\u00adjects\u201d and other terms with simi\u00adlar mea\u00adning. Inves\u00adtors are cau\u00adtio\u00adned that the for\u00adward-loo\u00adking state\u00adments in this press release are based on cur\u00adrent beliefs, assump\u00adti\u00adons and expec\u00adta\u00adti\u00adons, speak only as of the date of this press release and invol\u00adve risks and uncer\u00adtain\u00adties that could cau\u00adse actu\u00adal results to dif\u00adfer mate\u00adri\u00adal\u00adly from cur\u00adrent expec\u00adta\u00adti\u00adons. Such state\u00adments are sub\u00adject to cer\u00adtain known and unknown risks and uncer\u00adtain\u00adties, many of which are dif\u00adfi\u00adcult to pre\u00addict and gene\u00adral\u00adly bey\u00adond <span class=\"caps\">AMD<\/span>\u2019s con\u00adtrol, that could cau\u00adse actu\u00adal results and other future events to dif\u00adfer mate\u00adri\u00adal\u00adly from tho\u00adse expres\u00adsed in, or impli\u00aded or pro\u00adjec\u00adted by, the for\u00adward-loo\u00adking infor\u00adma\u00adti\u00adon and state\u00adments. Mate\u00adri\u00adal fac\u00adtors that could cau\u00adse actu\u00adal results to dif\u00adfer mate\u00adri\u00adal\u00adly from cur\u00adrent expec\u00adta\u00adti\u00adons include, wit\u00adhout limi\u00adta\u00adti\u00adon, the fol\u00adlo\u00adwing: Intel Corporation\u2019s domi\u00adnan\u00adce of the micro\u00adpro\u00adces\u00adsor mar\u00adket and its aggres\u00adsi\u00adve busi\u00adness prac\u00adti\u00adces; glo\u00adbal eco\u00adno\u00admic uncer\u00adtain\u00adty; cycli\u00adcal natu\u00adre of the semi\u00adcon\u00adduc\u00adtor indus\u00adtry; mar\u00adket con\u00addi\u00adti\u00adons of the indus\u00adtries in which <span class=\"caps\">AMD<\/span> pro\u00adducts are sold; loss of a signi\u00adfi\u00adcant cus\u00adto\u00admer; impact of the <span class=\"caps\">COVID-19<\/span> pan\u00adde\u00admic on <span class=\"caps\">AMD<\/span>\u2019s busi\u00adness, finan\u00adcial con\u00addi\u00adti\u00adon and results of ope\u00adra\u00adti\u00adons; com\u00adpe\u00adti\u00adti\u00adve mar\u00adkets in which <span class=\"caps\">AMD<\/span>\u2019s pro\u00adducts are sold; quar\u00adter\u00adly and sea\u00adso\u00adnal sales pat\u00adterns; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to ade\u00adqua\u00adte\u00adly pro\u00adtect its tech\u00adno\u00adlo\u00adgy or other intellec\u00adtu\u00adal pro\u00adper\u00adty; unfa\u00advorable cur\u00adren\u00adcy exch\u00adan\u00adge rate fluc\u00adtua\u00adtions; abili\u00adty of third par\u00adty manu\u00adfac\u00adtu\u00adr\u00aders to manu\u00adfac\u00adtu\u00adre <span class=\"caps\">AMD<\/span>\u2019s pro\u00adducts on a time\u00adly basis in suf\u00adfi\u00adci\u00adent quan\u00adti\u00adties and using com\u00adpe\u00adti\u00adti\u00adve tech\u00adno\u00adlo\u00adgies; avai\u00adla\u00adbi\u00adli\u00adty of essen\u00adti\u00adal equip\u00adment, mate\u00adri\u00adals, sub\u00adstra\u00adtes or manu\u00adfac\u00adtu\u00adring pro\u00adces\u00adses; abili\u00adty to achie\u00adve expec\u00adted manu\u00adfac\u00adtu\u00adring yields for <span class=\"caps\">AMD<\/span>\u2019s pro\u00adducts; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to intro\u00addu\u00adce pro\u00adducts on a time\u00adly basis with expec\u00adted fea\u00adtures and per\u00adfor\u00admance levels; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to gene\u00adra\u00adte reve\u00adnue from its semi-cus\u00adtom SoC pro\u00adducts; poten\u00adti\u00adal secu\u00adri\u00adty vul\u00adnerabi\u00adli\u00adties; poten\u00adti\u00adal secu\u00adri\u00adty inci\u00addents inclu\u00adding <span class=\"caps\">IT<\/span> outa\u00adges, data loss, data brea\u00adches and cyber-attacks; poten\u00adti\u00adal dif\u00adfi\u00adcul\u00adties in upgrading and ope\u00adra\u00adting <span class=\"caps\">AMD<\/span>\u2019s new enter\u00adpri\u00adse resour\u00adce plan\u00adning sys\u00adtem; uncer\u00adtain\u00adties invol\u00adving the orde\u00adring and ship\u00adment of <span class=\"caps\">AMD<\/span>\u2019s pro\u00adducts; <span class=\"caps\">AMD<\/span>\u2019s reli\u00adance on third-par\u00adty intellec\u00adtu\u00adal pro\u00adper\u00adty to design and intro\u00addu\u00adce new pro\u00adducts in a time\u00adly man\u00adner; <span class=\"caps\">AMD<\/span>\u2019s reli\u00adance on third-par\u00adty com\u00adpa\u00adnies for design, manu\u00adfac\u00adtu\u00adre and sup\u00adp\u00adly of mother\u00adboards, soft\u00adware and other com\u00adpu\u00adter plat\u00adform com\u00adpon\u00adents; <span class=\"caps\">AMD<\/span>\u2019s reli\u00adance on Micro\u00adsoft and other soft\u00adware ven\u00addors\u2019 sup\u00adport to design and deve\u00adlop soft\u00adware to run on <span class=\"caps\">AMD<\/span>\u2019s pro\u00adducts; <span class=\"caps\">AMD<\/span>\u2019s reli\u00adance on third-par\u00adty dis\u00adtri\u00adbu\u00adtors and add-in-board part\u00adners; impact of modi\u00adfi\u00adca\u00adti\u00adon or inter\u00adrup\u00adti\u00adon of <span class=\"caps\">AMD<\/span>\u2019s inter\u00adnal busi\u00adness pro\u00adces\u00adses and infor\u00adma\u00adti\u00adon sys\u00adtems; com\u00adpa\u00adti\u00adbi\u00adli\u00adty of <span class=\"caps\">AMD<\/span>\u2019s pro\u00adducts with some or all indus\u00adtry-stan\u00addard soft\u00adware and hard\u00adware; cos\u00adts rela\u00adted to defec\u00adti\u00adve pro\u00adducts; effi\u00adci\u00aden\u00adcy of <span class=\"caps\">AMD<\/span>\u2019s sup\u00adp\u00adly chain; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to rely on third par\u00adty sup\u00adp\u00adly-chain logi\u00adstics func\u00adtions; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to effec\u00adtively con\u00adtrol sales of its pro\u00adducts on the gray mar\u00adket; impact of govern\u00adment actions and regu\u00adla\u00adti\u00adons such as export admi\u00adnis\u00adtra\u00adti\u00adon regu\u00adla\u00adti\u00adons, tariffs and trade pro\u00adtec\u00adtion mea\u00adsu\u00adres; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to rea\u00adli\u00adze its defer\u00adred tax assets; poten\u00adti\u00adal tax lia\u00adbi\u00adli\u00adties; cur\u00adrent and future claims and liti\u00adga\u00adti\u00adon; impact of envi\u00adron\u00admen\u00adtal laws, con\u00adflict mine\u00adrals-rela\u00adted pro\u00advi\u00adsi\u00adons and other laws or regu\u00adla\u00adti\u00adons; impact of acqui\u00adsi\u00adti\u00adons, joint ven\u00adtures and\/or invest\u00adments on <span class=\"caps\">AMD<\/span>\u2019s busi\u00adness and <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to inte\u00adgra\u00adte acqui\u00adred busi\u00adnesses; impact of any impair\u00adment of the com\u00adbi\u00adned company\u2019s assets on the com\u00adbi\u00adned company\u2019s finan\u00adcial posi\u00adti\u00adon and results of ope\u00adra\u00adti\u00adon; rest\u00adric\u00adtions impo\u00adsed by agree\u00adments gover\u00adning <span class=\"caps\">AMD<\/span>\u2019s notes, the gua\u00adran\u00adtees of Xilinx\u2019s notes and the revol\u00adving cre\u00addit faci\u00adli\u00adty; <span class=\"caps\">AMD<\/span>\u2019s indeb\u00adted\u00adness; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to gene\u00adra\u00adte suf\u00adfi\u00adci\u00adent cash to meet its working capi\u00adtal requi\u00adre\u00adments or gene\u00adra\u00adte suf\u00adfi\u00adci\u00adent reve\u00adnue and ope\u00adra\u00adting cash flow to make all of its plan\u00adned R<span class=\"amp\">&amp;<\/span>D or stra\u00adte\u00adgic invest\u00adments; poli\u00adti\u00adcal, legal, eco\u00adno\u00admic risks and natu\u00adral dis\u00adas\u00adters; future impairm\u00adents of good\u00adwill and tech\u00adno\u00adlo\u00adgy licen\u00adse purcha\u00adses; <span class=\"caps\">AMD<\/span>\u2019s abili\u00adty to attract and retain qua\u00adli\u00adfied per\u00adson\u00adnel; <span class=\"caps\">AMD<\/span>\u2019s stock pri\u00adce vola\u00adti\u00adli\u00adty; and world\u00adwi\u00adde poli\u00adti\u00adcal con\u00addi\u00adti\u00adons. Inves\u00adtors are urged to review in detail the risks and uncer\u00adtain\u00adties in <span class=\"caps\">AMD<\/span>\u2019s Secu\u00adri\u00adties and Exch\u00adan\u00adge Com\u00admis\u00adsi\u00adon filings, inclu\u00adding but not limi\u00adt\u00aded to <span class=\"caps\">AMD<\/span>\u2019s most recent reports on Forms 10\u2011K and 10\u2011Q.<\/p>\n","protected":false},"excerpt":{"rendered":"<p><\/p><p align=\"left\"><span class=\"caps\">SANTA<\/span> <span class=\"caps\">CLARA<\/span>, Calif., April 20, 2023 (<span class=\"caps\">GLOBE<\/span> <span class=\"caps\">NEWSWIRE<\/span>) \u2014&nbsp;<a title=\"AMD\" href=\"http:\/\/www.amd.com\/\" target=\"_blank\" rel=\"nofollow noopener\"><span class=\"caps\">AMD<\/span><\/a>&nbsp;(<span class=\"caps\">NASDAQ<\/span>: <span class=\"caps\">AMD<\/span>) today announ\u00adced the avai\u00adla\u00adbi\u00adli\u00adty of its high-per\u00adfor\u00admance <span class=\"caps\">AMD<\/span> Ryzen\u2122 Embedded 5000 Series, a new solu\u00adti\u00adon for cus\u00adto\u00admers requi\u00adring power-effi\u00adci\u00adent pro\u00adces\u00adsors opti\u00admi\u00adzed for \u201calways on\u201d net\u00adwor\u00adking fire\u00adwalls, net\u00adwork-atta\u00adched sto\u00adrage sys\u00adtems and other secu\u00adri\u00adty appli\u00adca\u00adti\u00adons. The Ryzen Embedded 5000 Series rounds out the \u201cZen 3\u201d-based <span class=\"caps\">AMD<\/span> embedded pro\u00adces\u00adsor port\u00adfo\u00adlio which also includes the Ryzen Embedded <span class=\"caps\">V3000<\/span> and <span class=\"caps\">EPYC<\/span>\u2122 Embedded 7000 series families.<\/p>\n<p>Built on 7nm tech\u00adno\u00adlo\u00adgy with plan\u00adned five-year manu\u00adfac\u00adtu\u00adring avai\u00adla\u00adbi\u00adli\u00adty, and equip\u00adped with 6, 8, 12 or 16 cores and 24 lanes of PCIe\u00ae Gen4 con\u00adnec\u00adti\u00advi\u00adty, Ryzen Embedded 5000 Series pro\u00adces\u00adsors are desi\u00adgned for enter\u00adpri\u00adse relia\u00adbi\u00adli\u00adty to sup\u00adport the con\u00adsis\u00adtent uptime requi\u00adre\u00adments nee\u00added by secu\u00adri\u00adty and net\u00adwor\u00adking cus\u00adto\u00admers. Ryzen Embedded 5000 Series pro\u00adces\u00adsors include robust relia\u00adbi\u00adli\u00adty, avai\u00adla\u00adbi\u00adli\u00adty and ser\u00advicea\u00adbi\u00adli\u00adty (<span class=\"caps\">RAS<\/span>) fea\u00adtures, inclu\u00adding an ECC-sup\u00adport\u00aded memo\u00adry sub\u00adsys\u00adtem. With a ther\u00admal design power (<span class=\"caps\">TDP<\/span>) pro\u00adfi\u00adle ran\u00adging from <span class=\"caps\">65W<\/span> to <span class=\"caps\">105W<\/span>, Ryzen Embedded 5000 pro\u00adces\u00adsors enable the reduc\u00adtion of over\u00adall sys\u00adtem coo\u00adling foot\u00adprint for space-cons\u00adtrai\u00adned and cost-sen\u00adsi\u00adti\u00adve appli\u00adca\u00adti\u00adons. (\u2026) <a class=\"moretag\" href=\"https:\/\/www.planet3dnow.de\/cms\/67906-amd-bolsters-embedded-portfolio-with-new-ryzen-embedded-5000-series-processors-for-networking-solutions\/\">Wei\u00adter\u00adle\u00adsen&nbsp;\u00bb<\/a><\/p>\n","protected":false},"author":593,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[966,106,2849],"class_list":["post-67906","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","tag-amd","tag-embedded","tag-ryzen-embedded-5000","entry"],"share_on_mastodon":{"url":"","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/67906","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/593"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=67906"}],"version-history":[{"count":1,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/67906\/revisions"}],"predecessor-version":[{"id":67907,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/67906\/revisions\/67907"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=67906"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=67906"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=67906"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}