{"id":67972,"date":"2023-07-02T22:23:44","date_gmt":"2023-07-02T20:23:44","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=67972"},"modified":"2023-07-02T22:23:44","modified_gmt":"2023-07-02T20:23:44","slug":"amd-introduces-worlds-largest-fpga-based-adaptive-soc-for-emulation-and-prototyping","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/67972-amd-introduces-worlds-largest-fpga-based-adaptive-soc-for-emulation-and-prototyping\/","title":{"rendered":"AMD<\/span> Introduces World\u2019s Largest FPGA-Based Adaptive SoC for Emulation and Prototyping"},"content":{"rendered":"

\ua7f7 AMD<\/span> Ver\u00adsal Pre\u00admi\u00adum VP1902<\/span> adap\u00adti\u00adve SoC offers 2X<\/span> the capa\u00adci\u00adty of pre\u00advious-gene\u00adra\u00adti\u00adon FPGAs, pro\u00advi\u00adding chip\u00adma\u00adkers with the tools to bring new ASIC<\/span> and SoC designs to mar\u00adket fas\u00adter <\/em>\u2500<\/p>\n

\ua7f7 Col\u00adla\u00adbo\u00adra\u00adti\u00adon with EDA<\/span> lea\u00adders Cadence, Sie\u00admens and Syn\u00adop\u00adsys helps ensu\u00adre chip desi\u00adgners have access to sca\u00adlable eco\u00adsys\u00adtem of ful\u00adly-fea\u00adtured solu\u00adti\u00adons <\/em>\ua7f7<\/p>\n

SANTA<\/span> CLARA<\/span>, Calif., June 27, 2023 (GLOBE<\/span> NEWSWIRE<\/span>) \u2014 AMD<\/span><\/u><\/a> (NASDAQ<\/span>: AMD<\/span>) today announ\u00adced the AMD<\/span> Ver\u00adsal\u2122 Pre\u00admi\u00adum VP1902<\/span><\/a> adap\u00adti\u00adve sys\u00adtem-on-chip (SoC), the world\u2019s lar\u00adgest1<\/sup> adap\u00adti\u00adve SoC. The VP1902<\/span> adap\u00adti\u00adve SoC is an emu\u00adla\u00adti\u00adon-class, chip\u00adlet-based device desi\u00adgned to stream\u00adli\u00adne the veri\u00adfi\u00adca\u00adti\u00adon of incre\u00adasing\u00adly com\u00adplex semi\u00adcon\u00adduc\u00adtor designs. Offe\u00adring 2X<\/span>2<\/sup> the capa\u00adci\u00adty over the pri\u00ador gene\u00adra\u00adti\u00adon, desi\u00adgners can con\u00adfi\u00addent\u00adly inno\u00adva\u00adte and vali\u00adda\u00adte appli\u00adca\u00adti\u00adon-spe\u00adci\u00adfic inte\u00adgra\u00adted cir\u00adcuits (ASICs) and SoC designs to help bring next gene\u00adra\u00adti\u00adon tech\u00adno\u00adlo\u00adgies to mar\u00adket faster.
\nAI<\/span> workloads are dri\u00adving increased com\u00adple\u00adxi\u00adty in chip\u00adma\u00adking, requi\u00adring next-gene\u00adra\u00adti\u00adon solu\u00adti\u00adons to deve\u00adlop the chips of tomor\u00adrow. FPGA-based emu\u00adla\u00adti\u00adon and pro\u00adto\u00adty\u00adp\u00ading pro\u00advi\u00addes the hig\u00adhest level of per\u00adfor\u00admance, allo\u00adwing fas\u00adter sili\u00adcon veri\u00adfi\u00adca\u00adti\u00adon and enab\u00adling deve\u00adlo\u00adpers to shift left in the design cycle and begin soft\u00adware deve\u00adlo\u00adp\u00adment well befo\u00adre sili\u00adcon tape-out. AMD<\/span>, through Xilinx, brings over 17 years of lea\u00adder\u00adship and six gene\u00adra\u00adti\u00adons of the industry\u2019s hig\u00adhest capa\u00adci\u00adty emu\u00adla\u00adti\u00adon devices, which have near\u00adly dou\u00adbled in capa\u00adci\u00adty each gene\u00adra\u00adti\u00adon3<\/sup>.
\n\u201cDeli\u00adve\u00adring foun\u00adda\u00adtio\u00adnal com\u00adpu\u00adte tech\u00adno\u00adlo\u00adgy to enable our cus\u00adto\u00admers is a top prio\u00adri\u00adty. In emu\u00adla\u00adti\u00adon and pro\u00adto\u00adty\u00adp\u00ading, that means deli\u00adve\u00adring the hig\u00adhest capa\u00adci\u00adty and per\u00adfor\u00admance pos\u00adsi\u00adble,\u201d said Kirk Saban, cor\u00adpo\u00adra\u00adte vice pre\u00adsi\u00addent, Pro\u00adduct, Soft\u00adware, &<\/span> Solu\u00adti\u00adons Mar\u00adke\u00adting, Adap\u00adti\u00adve and Embedded Com\u00adpu\u00adting Group, AMD<\/span>. \u201cChip desi\u00adgners can con\u00adfi\u00addent\u00adly emu\u00adla\u00adte and pro\u00adto\u00adty\u00adpe next-gene\u00adra\u00adti\u00adon pro\u00adducts using our VP1902<\/span> adap\u00adti\u00adve SoC, acce\u00adle\u00adra\u00adting tomorrow\u2019s inno\u00adva\u00adtions in AI<\/span>, auto\u00adno\u00admous vehic\u00adles, Indus\u00adtry 5.0 and other emer\u00adging technologies.\u201d<\/p>\n

Con\u00adfi\u00addent\u00adly Emu\u00adla\u00adte and Pro\u00adto\u00adty\u00adpe Next-Gene\u00adra\u00adti\u00adon Designs<\/strong>
\nAs com\u00adple\u00adxi\u00adty grows in ASIC<\/span> and SoC designs, espe\u00adci\u00adal\u00adly with the rapid advance\u00adment of AI<\/span> and ML-based chips, exten\u00adsi\u00adve veri\u00adfi\u00adca\u00adti\u00adon of both sili\u00adcon and soft\u00adware befo\u00adre tape-out is a must.
\nThe VP1902<\/span> deli\u00advers indus\u00adtry lea\u00adding capa\u00adci\u00adty and con\u00adnec\u00adti\u00advi\u00adty, deli\u00adve\u00adring 18.5M<\/span> logic cells for 2X<\/span>2<\/sup> hig\u00adher pro\u00adgramma\u00adble logic den\u00adsi\u00adty and 2X<\/span>4<\/sup> aggre\u00adga\u00adte I\/O band\u00adwidth com\u00adpared to the pre\u00advious gene\u00adra\u00adti\u00adon Vir\u00adtex\u2122 UltraS\u00adca\u00adle+\u2122 VU19P<\/span> FPGA<\/span>.<\/p>\n

Ite\u00adra\u00adte Designs Fast with Unmat\u00adched Debug Capabilities
\n<\/strong>Debug is essen\u00adti\u00adal for pre-sili\u00adcon veri\u00adfi\u00adca\u00adti\u00adon and con\u00adcur\u00adrent soft\u00adware deve\u00adlo\u00adp\u00adment. Fin\u00adding and addres\u00adsing bugs befo\u00adre tape-out keeps pro\u00adgrams on sche\u00addu\u00adle and bud\u00adget. The VP1902<\/span> adap\u00adti\u00adve SoC lever\u00ada\u00adges the Ver\u00adsal archi\u00adtec\u00adtu\u00adre, inclu\u00adding the pro\u00adgramma\u00adble net\u00adwork-on-chip, to pro\u00advi\u00adde up to 8X<\/span>5<\/sup> fas\u00adter debug\u00adging com\u00adpared to the pri\u00ador gene\u00adra\u00adti\u00adon VU19P<\/span> FPGA<\/span>.<\/p>\n

Deve\u00adlo\u00adp\u00adment Tools and Eco\u00adsys\u00adtem Collaborations<\/strong>
\nThe AMD<\/span> Viv\u00ada\u00addo\u2122 ML<\/span><\/a> design suite pro\u00advi\u00addes cus\u00adto\u00admers with a com\u00adpre\u00adhen\u00adsi\u00adve deve\u00adlo\u00adp\u00adment plat\u00adform to quick\u00adly design, debug and vali\u00adda\u00adte next-gene\u00adra\u00adti\u00adon appli\u00adca\u00adti\u00adons and tech\u00adno\u00adlo\u00adgies and acce\u00adle\u00adra\u00adte time to mar\u00adket. New fea\u00adtures that sup\u00adport more effi\u00adci\u00adent deve\u00adlo\u00adp\u00adment on the VP1902<\/span> adap\u00adti\u00adve SoC include auto\u00adma\u00adted design clo\u00adsure assis\u00adtance, inter\u00adac\u00adti\u00adve design tuning, remo\u00adte mul\u00adti-user real-time debug\u00adging, and enhan\u00adced back-end com\u00adpi\u00adla\u00adti\u00adon, which enables end users to ite\u00adra\u00adte IC<\/span> designs faster. 
\nAMD<\/span> col\u00adla\u00adbo\u00adra\u00adtes clo\u00adse\u00adly with the EDA<\/span> com\u00admu\u00adni\u00adty to help cus\u00adto\u00admers turn their inno\u00adva\u00adtions and tech\u00adno\u00adlo\u00adgy visi\u00adon into rea\u00adli\u00adty. Working clo\u00adse\u00adly with the top EDA<\/span> ven\u00addors, inclu\u00adding Cadence, Sie\u00admens and Syn\u00adop\u00adsys helps desi\u00adgners access an eco\u00adsys\u00adtem of ful\u00adly-fea\u00adtured and sca\u00adlable solutions.
\nThe AMD<\/span> Ver\u00adsal Pre\u00admi\u00adum VP1902<\/span> adap\u00adti\u00adve SoC will begin sam\u00adpling in Q3<\/span> to ear\u00adly access cus\u00adto\u00admers with pro\u00adduc\u00adtion expec\u00adted in the first half of 2024.<\/p>\n

Sup\u00adport\u00ading Resources<\/strong><\/p>\n