{"id":68276,"date":"2026-06-01T11:48:51","date_gmt":"2026-06-01T09:48:51","guid":{"rendered":"https:\/\/www.planet3dnow.de\/cms\/?p=68276"},"modified":"2026-06-01T11:48:51","modified_gmt":"2026-06-01T09:48:51","slug":"amd-announces-production-ramp-of-next-generation-amd-epyc-processor","status":"publish","type":"post","link":"https:\/\/www.planet3dnow.de\/cms\/68276-amd-announces-production-ramp-of-next-generation-amd-epyc-processor\/","title":{"rendered":"AMD<\/span> Announces Production Ramp of Next-Generation AMD<\/span> EPYC<\/span> Processor \u201cVenice\u201d on TSMC<\/span> 2nm Process Technology"},"content":{"rendered":"

News Sum\u00adma\u00adry:<\/strong><\/p>\n

    \n
  • AMD<\/span> has begun pro\u00adduc\u00adtion ramp of its 6th Gen AMD<\/span> EPYC<\/span>\u2122 CPUs, code\u00adna\u00admed \u201cVenice,\u201d mar\u00adking a major mile\u00adstone for the AMD<\/span> and TSMC<\/span> col\u00adla\u00adbo\u00adra\u00adti\u00adon on 2nm technology<\/li>\n
  • \u201c<\/span>Venice\u201d is the first HPC<\/span> pro\u00adduct in the indus\u00adtry to achie\u00adve pro\u00adduc\u00adtion ramp on TSMC<\/span> advan\u00adced 2nm technology<\/li>\n
  • Cri\u00adti\u00adcal mile\u00adstone achie\u00adved as agen\u00adtic AI<\/span> workloads dri\u00adve demand for acce\u00adle\u00adra\u00adted AI<\/span> infra\u00adstruc\u00adtu\u00adre deployments<\/li>\n
  • AMD<\/span> con\u00adti\u00adnues to dri\u00adve 2nm pro\u00adduct expan\u00adsi\u00adon with \u201cVer\u00adano\u201d a fol\u00adlow on to \u201cVenice\u201d with indus\u00adtry lea\u00adding inte\u00adgra\u00adti\u00adon of LPDDR<\/span> for gro\u00adwing memo\u00adry demand in agen\u00adtic AI<\/span> workloads<\/li>\n<\/ul>\n

    SANTA<\/span> CLARA<\/span>, Calif., May 21, 2026 (GLOBE<\/span> NEWSWIRE<\/span>) \u2014 AMD<\/span> (NASDAQ<\/span>: AMD<\/span>) today announ\u00adced that its next-gene\u00adra\u00adti\u00adon AMD<\/span> EPYC<\/span>\u2122 pro\u00adces\u00adsor, code\u00adna\u00admed \u201cVenice,\u201d is ram\u00adping pro\u00adduc\u00adtion in Tai\u00adwan on TSMC<\/span>\u2019s advan\u00adced 2nm pro\u00adcess tech\u00adno\u00adlo\u00adgy, with future plans to ramp pro\u00adduc\u00adtion at TSMC<\/span>\u2019s Ari\u00adzo\u00adna fabri\u00adca\u00adti\u00adon faci\u00adli\u00adty. The mile\u00adstone in the exe\u00adcu\u00adti\u00adon of the AMD<\/span> data cen\u00adter CPU<\/span> road\u00admap demons\u00adtra\u00adtes con\u00adtin\u00adued pro\u00adgress toward deli\u00adve\u00adring the lea\u00adder\u00adship per\u00adfor\u00admance and ener\u00adgy effi\u00adci\u00aden\u00adcy requi\u00adred for next-gene\u00adra\u00adti\u00adon cloud, enter\u00adpri\u00adse and AI<\/span> infra\u00adstruc\u00adtu\u00adre. \u201cVenice\u201d is the first high-per\u00adfor\u00admance com\u00adpu\u00adting (HPC<\/span>) pro\u00adduct in the indus\u00adtry to enter pro\u00adduc\u00adtion on TSMC<\/span>\u2019s advan\u00adced 2nm pro\u00adcess technology.<\/p>\n

    \u201c<\/span>Ram\u00adping \u2018Venice\u2019 on TSMC<\/span> 2nm pro\u00adcess tech\u00adno\u00adlo\u00adgy marks an important step for\u00adward in acce\u00adle\u00adra\u00adting the next gene\u00adra\u00adti\u00adon of AI<\/span> infra\u00adstruc\u00adtu\u00adre,\u201d said Dr. Lisa Su, chair and CEO<\/span>, AMD<\/span>. \u201cAs AI<\/span> and agen\u00adtic workloads sca\u00adle rapidly, cus\u00adto\u00admers need plat\u00adforms that can move from inno\u00adva\u00adti\u00adon to pro\u00adduc\u00adtion fas\u00adter. Our deep part\u00adner\u00adship with TSMC<\/span> is hel\u00adping AMD<\/span> bring lea\u00adder\u00adship com\u00adpu\u00adte tech\u00adno\u00adlo\u00adgies to mar\u00adket with the speed and sca\u00adle requi\u00adred to meet this moment.\u201d<\/p>\n

    As AI<\/span> adop\u00adti\u00adon expands from trai\u00adning and infe\u00adrence to incre\u00adasing\u00adly com\u00adplex agen\u00adtic workloads, the CPU<\/span> is beco\u00adming even more cri\u00adti\u00adcal to sca\u00adling AI<\/span> infra\u00adstruc\u00adtu\u00adre, coor\u00addi\u00adna\u00adting data move\u00adment, net\u00adwor\u00adking, sto\u00adrage, secu\u00adri\u00adty and sys\u00adtem orchestra\u00adti\u00adon across the data cen\u00adter. The ramp of \u201cVenice\u201d comes as AMD<\/span> con\u00adti\u00adnues to build momen\u00adtum in the ser\u00adver mar\u00adket, reflec\u00adting gro\u00adwing cus\u00adto\u00admer demand for EPYC<\/span> pro\u00adces\u00adsors to power modern cloud, enter\u00adpri\u00adse, HPC<\/span> and AI<\/span> deployments.<\/p>\n

    The \u201cVenice\u201d ramp in Tai\u00adwan and plans to ramp at TSMC<\/span> Ari\u00adzo\u00adna reflect AMD<\/span>\u2019s focus on streng\u00adthening its geo\u00adgra\u00adphi\u00adcal\u00adly diver\u00adse advan\u00adced manu\u00adfac\u00adtu\u00adring foot\u00adprint. By pai\u00adring next-gene\u00adra\u00adti\u00adon EPYC<\/span> pro\u00adces\u00adsor inno\u00adva\u00adti\u00adon with advan\u00adced manu\u00adfac\u00adtu\u00adring capa\u00adci\u00adty across the glo\u00adbe, AMD<\/span> is expan\u00adding the foun\u00adda\u00adti\u00adon nee\u00added to sup\u00adport cus\u00adto\u00admers as they deploy and sca\u00adle AI<\/span> infrastructure.<\/p>\n

    \u201c<\/span>We are plea\u00adsed to see AMD<\/span> con\u00adti\u00adnue to make strong pro\u00adgress with its next-gene\u00adra\u00adti\u00adon EPYC<\/span> pro\u00adces\u00adsor on our advan\u00adced 2nm pro\u00adcess tech\u00adno\u00adlo\u00adgy,\u201d said Dr. C.C. Wei, Chair\u00adman and CEO<\/span>, TSMC<\/span>. \u201cOur clo\u00adse col\u00adla\u00adbo\u00adra\u00adti\u00adon with AMD<\/span> reflects the importance of pai\u00adring lea\u00adder\u00adship pro\u00adcess tech\u00adno\u00adlo\u00adgy with advan\u00adced design inno\u00adva\u00adti\u00adon to enable the next era of high-per\u00adfor\u00admance and AI<\/span> computing.\u201d<\/p>\n

    AMD<\/span> also plans to extend TSMC<\/span> 2nm pro\u00adcess tech\u00adno\u00adlo\u00adgy across its data cen\u00adter CPU<\/span> road\u00admap with \u201cVer\u00adano,\u201d a 6th Gen EPYC<\/span> pro\u00adces\u00adsor opti\u00admi\u00adzed for per\u00adfor\u00admance-per-dol\u00adlar-per-watt lea\u00adder\u00adship. Desi\u00adgned to sup\u00adport cloud and AI<\/span> com\u00adpu\u00adting workloads, \u201cVer\u00adano\u201d is expec\u00adted to build on the AMD<\/span> EPYC<\/span> plat\u00adform with advan\u00adced memo\u00adry inno\u00adva\u00adtions, inclu\u00adding LPDDR<\/span>, to deli\u00adver the CPU<\/span> per\u00adfor\u00admance, band\u00adwidth and effi\u00adci\u00aden\u00adcy requi\u00adred for incre\u00adasing\u00adly power cons\u00adtrai\u00adned workloads and applications.<\/p>\n

    AMD<\/span> and TSMC<\/span>\u2019s part\u00adner\u00adship spans the tech\u00adno\u00adlo\u00adgies nee\u00added to sca\u00adle modern data cen\u00adter com\u00adpu\u00adting, from TSMC<\/span> 2nm pro\u00adcess tech\u00adno\u00adlo\u00adgy for next-gene\u00adra\u00adti\u00adon CPUs to advan\u00adced pack\u00ada\u00adging tech\u00adno\u00adlo\u00adgies, inclu\u00adding TSMC<\/span>\u2019s SoIC\u00ae-X and CoWoS\u00ae-L, used across AMD<\/span>\u2019s broa\u00adder AI<\/span> and data cen\u00adter port\u00adfo\u00adlio. With \u201cVenice\u201d ram\u00adping on TSMC<\/span> 2nm, AMD<\/span> is advan\u00adcing the CPU<\/span> foun\u00adda\u00adti\u00adon for AI<\/span> infra\u00adstruc\u00adtu\u00adre while con\u00adti\u00adnuing to levera\u00adge TSMC<\/span>\u2019s pro\u00adcess and pack\u00ada\u00adging lea\u00adder\u00adship to deli\u00adver incre\u00adasing\u00adly inte\u00adgra\u00adted com\u00adpu\u00adte plat\u00adforms at scale.<\/p>\n

    About AMD<\/span><\/strong><\/p>\n

    AMD<\/span> (NASDAQ<\/span>: AMD<\/span>) dri\u00adves inno\u00adva\u00adti\u00adon in high-per\u00adfor\u00admance and AI<\/span> com\u00adpu\u00adting to sol\u00adve the world\u2019s most important chal\u00adlenges. Today, AMD<\/span> tech\u00adno\u00adlo\u00adgy powers bil\u00adli\u00adons of expe\u00adri\u00aden\u00adces across cloud and AI<\/span> infra\u00adstruc\u00adtu\u00adre, embedded sys\u00adtems, AI<\/span> PCs and gam\u00ading. With a broad port\u00adfo\u00adlio of AI-opti\u00admi\u00adzed CPUs, GPUs, net\u00adwor\u00adking and soft\u00adware, AMD<\/span> deli\u00advers full-stack AI<\/span> solu\u00adti\u00adons that pro\u00advi\u00adde the per\u00adfor\u00admance and sca\u00adla\u00adbi\u00adli\u00adty nee\u00added for a new era of intel\u00adli\u00adgent com\u00adpu\u00adting. Learn more at www.amd.com.<\/p>\n

    Cau\u00adtio\u00adna\u00adry Statement<\/strong><\/p>\n

    This press release con\u00adta\u00adins for\u00adward-loo\u00adking state\u00adments con\u00adcer\u00adning Advan\u00adced Micro Devices, Inc. (AMD<\/span>) such as the ram\u00adping of AMD<\/span>\u2019s 6th Gen AMD<\/span> EPYC<\/span>\u2122 CPUs and future plans and expec\u00adta\u00adti\u00adons of its part\u00adner\u00adship with TSMC<\/span>, which are made pur\u00adsu\u00adant to the Safe Har\u00adbor pro\u00advi\u00adsi\u00adons of the Pri\u00adva\u00adte Secu\u00adri\u00adties Liti\u00adga\u00adti\u00adon Reform Act of 1995. For\u00adward-loo\u00adking state\u00adments are com\u00admon\u00adly iden\u00adti\u00adfied by words such as \u201cwould,\u201d \u201cmay,\u201d \u201cexpects,\u201d \u201cbelie\u00adves,\u201d \u201cplans,\u201d \u201cintends,\u201d \u201cpro\u00adjects\u201d and other terms with simi\u00adlar mea\u00adning. Inves\u00adtors are cau\u00adtio\u00adned that the for\u00adward-loo\u00adking state\u00adments in this press release are based on cur\u00adrent beliefs, assump\u00adti\u00adons and expec\u00adta\u00adti\u00adons, speak only as of the date of this press release and invol\u00adve risks and uncer\u00adtain\u00adties that could cau\u00adse actu\u00adal results to dif\u00adfer mate\u00adri\u00adal\u00adly from cur\u00adrent expec\u00adta\u00adti\u00adons. Such state\u00adments are sub\u00adject to cer\u00adtain known and unknown risks and uncer\u00adtain\u00adties, many of which are dif\u00adfi\u00adcult to pre\u00addict and are gene\u00adral\u00adly bey\u00adond AMD<\/span>\u2019s con\u00adtrol, that could cau\u00adse actu\u00adal results and other future events to dif\u00adfer mate\u00adri\u00adal\u00adly from tho\u00adse expres\u00adsed in, or impli\u00aded or pro\u00adjec\u00adted by, the for\u00adward-loo\u00adking infor\u00adma\u00adti\u00adon and state\u00adments. Mate\u00adri\u00adal fac\u00adtors that could cau\u00adse actu\u00adal results to dif\u00adfer mate\u00adri\u00adal\u00adly from cur\u00adrent expec\u00adta\u00adti\u00adons include, wit\u00adhout limi\u00adta\u00adti\u00adon, the fol\u00adlo\u00adwing: impact of govern\u00adment actions and regu\u00adla\u00adti\u00adons such as export regu\u00adla\u00adti\u00adons, import tariffs, trade pro\u00adtec\u00adtion mea\u00adsu\u00adres, and licen\u00adsing requi\u00adre\u00adments; com\u00adpe\u00adti\u00adti\u00adve mar\u00adkets in which AMD<\/span>\u2019s pro\u00adducts are sold; the cycli\u00adcal natu\u00adre of the semi\u00adcon\u00adduc\u00adtor indus\u00adtry; mar\u00adket con\u00addi\u00adti\u00adons of the indus\u00adtries in which AMD<\/span> pro\u00adducts are sold; AMD<\/span>\u2019s abili\u00adty to intro\u00addu\u00adce pro\u00adducts on a time\u00adly basis with expec\u00adted fea\u00adtures and per\u00adfor\u00admance levels; loss of a signi\u00adfi\u00adcant cus\u00adto\u00admer; eco\u00adno\u00admic and mar\u00adket uncer\u00adtain\u00adty; quar\u00adter\u00adly and sea\u00adso\u00adnal sales pat\u00adterns; AMD<\/span>\u2019s abili\u00adty to ade\u00adqua\u00adte\u00adly pro\u00adtect its tech\u00adno\u00adlo\u00adgy or other intellec\u00adtu\u00adal pro\u00adper\u00adty; unfa\u00advorable cur\u00adren\u00adcy exch\u00adan\u00adge rate fluc\u00adtua\u00adtions; abili\u00adty of third par\u00adty manu\u00adfac\u00adtu\u00adr\u00aders to manu\u00adfac\u00adtu\u00adre AMD<\/span>\u2019s pro\u00adducts on a time\u00adly basis in suf\u00adfi\u00adci\u00adent quan\u00adti\u00adties and using com\u00adpe\u00adti\u00adti\u00adve tech\u00adno\u00adlo\u00adgies; avai\u00adla\u00adbi\u00adli\u00adty of essen\u00adti\u00adal equip\u00adment, mate\u00adri\u00adals, com\u00adpon\u00adents (such as memo\u00adry sup\u00adp\u00adly), sub\u00adstra\u00adtes or manu\u00adfac\u00adtu\u00adring pro\u00adces\u00adses; abili\u00adty to achie\u00adve expec\u00adted manu\u00adfac\u00adtu\u00adring yields for AMD<\/span>\u2019s pro\u00adducts; AMD<\/span>\u2019s abili\u00adty to gene\u00adra\u00adte reve\u00adnue from its semi-cus\u00adtom SoC pro\u00adducts; poten\u00adti\u00adal secu\u00adri\u00adty vul\u00adnerabi\u00adli\u00adties; poten\u00adti\u00adal secu\u00adri\u00adty inci\u00addents inclu\u00adding IT<\/span> outa\u00adges, data loss, data brea\u00adches and cyber\u00adat\u00adtacks; uncer\u00adtain\u00adties invol\u00adving the orde\u00adring and ship\u00adment of AMD<\/span>\u2019s pro\u00adducts; AMD<\/span>\u2019s reli\u00adance on third-par\u00adty intellec\u00adtu\u00adal pro\u00adper\u00adty to design and intro\u00addu\u00adce new pro\u00adducts; AMD<\/span>\u2019s reli\u00adance on third-par\u00adty com\u00adpa\u00adnies for design, manu\u00adfac\u00adtu\u00adre and sup\u00adp\u00adly of mother\u00adboards, soft\u00adware, memo\u00adry and other com\u00adpu\u00adter plat\u00adform com\u00adpon\u00adents; AMD<\/span>\u2019s reli\u00adance on Micro\u00adsoft and other soft\u00adware ven\u00addors\u2019 sup\u00adport to design and deve\u00adlop soft\u00adware to run on AMD<\/span>\u2019s pro\u00adducts; AMD<\/span>\u2019s reli\u00adance on third-par\u00adty dis\u00adtri\u00adbu\u00adtors and add-in-board part\u00adners; impact of modi\u00adfi\u00adca\u00adti\u00adon or inter\u00adrup\u00adti\u00adon of AMD<\/span>\u2019s inter\u00adnal busi\u00adness pro\u00adces\u00adses and infor\u00adma\u00adti\u00adon sys\u00adtems; com\u00adpa\u00adti\u00adbi\u00adli\u00adty of AMD<\/span>\u2019s pro\u00adducts with some or all indus\u00adtry-stan\u00addard soft\u00adware and hard\u00adware; cos\u00adts rela\u00adted to defec\u00adti\u00adve pro\u00adducts; fail\u00adure to main\u00adtain an effi\u00adci\u00adent sup\u00adp\u00adly chain as cus\u00adto\u00admer demand chan\u00adges; AMD<\/span>\u2019s abili\u00adty to rely on third par\u00adty sup\u00adp\u00adly-chain logi\u00adstics func\u00adtions; AMD<\/span>\u2019s abili\u00adty to effec\u00adtively con\u00adtrol sales of its pro\u00adducts on the gray mar\u00adket; impact of cli\u00adma\u00adte chan\u00adge on AMD<\/span>\u2019s busi\u00adness; AMD<\/span>\u2019s abili\u00adty to rea\u00adli\u00adze its defer\u00adred tax assets; poten\u00adti\u00adal tax lia\u00adbi\u00adli\u00adties; cur\u00adrent and future claims and liti\u00adga\u00adti\u00adon; impact of envi\u00adron\u00admen\u00adtal laws, con\u00adflict mine\u00adrals rela\u00adted pro\u00advi\u00adsi\u00adons and other laws or regu\u00adla\u00adti\u00adons; evol\u00adving expec\u00adta\u00adti\u00adons from govern\u00adments, inves\u00adtors, cus\u00adto\u00admers and other stake\u00adhol\u00adders regar\u00adding cor\u00adpo\u00adra\u00adte respon\u00adsi\u00adbi\u00adli\u00adty mat\u00adters; issues rela\u00adted to the respon\u00adsi\u00adble use of AI<\/span>; rest\u00adric\u00adtions impo\u00adsed by agree\u00adments gover\u00adning AMD<\/span>\u2019s notes, the gua\u00adran\u00adtees of Xilinx\u2019s notes and the revol\u00adving cre\u00addit agree\u00adment; AMD<\/span>\u2019s abili\u00adty to satis\u00adfy finan\u00adcial obli\u00adga\u00adti\u00adons under gua\u00adran\u00adtees, lea\u00adses and other com\u00admer\u00adcial com\u00admit\u00adments; impact of acqui\u00adsi\u00adti\u00adons, joint ven\u00adtures and\/or invest\u00adments on AMD<\/span>\u2019s busi\u00adness and AMD<\/span>\u2019s abili\u00adty to inte\u00adgra\u00adte acqui\u00adred busi\u00adnesses; impact of any impair\u00adment of the com\u00adbi\u00adned company\u2019s assets; poli\u00adti\u00adcal, legal and eco\u00adno\u00admic risks and natu\u00adral dis\u00adas\u00adters; future impairm\u00adents of tech\u00adno\u00adlo\u00adgy licen\u00adse purcha\u00adses; AMD<\/span>\u2019s abili\u00adty to attract and retain key employees; and AMD<\/span>\u2019s stock pri\u00adce vola\u00adti\u00adli\u00adty. Inves\u00adtors are urged to review in detail the risks and uncer\u00adtain\u00adties in AMD<\/span>\u2019s Secu\u00adri\u00adties and Exch\u00adan\u00adge Com\u00admis\u00adsi\u00adon filings, inclu\u00adding but not limi\u00adt\u00aded to AMD<\/span>\u2019s most recent reports on Forms 10\u2011K and 10\u2011Q.<\/p>\n","protected":false},"excerpt":{"rendered":"

    <\/p>

    \u2014 Next-gene\u00adra\u00adti\u00adon AMD<\/span> EPYC<\/span> CPU<\/span>, code\u00adna\u00admed \u201cVenice,\u201d is the first HPC<\/span> pro\u00adduct to be brought up on TSMC<\/span>\u2019s next-gene\u00adra\u00adti\u00adon N2<\/span> node \u2014<\/em><\/p>\n

    SANTA<\/span> CLARA<\/span>, Calif., April 14, 2025 (GLOBE<\/span> NEWSWIRE<\/span>) \u2014 AMD<\/span><\/a> (NASDAQ<\/span>: AMD<\/span>) today announ\u00adced its next-gene\u00adra\u00adti\u00adon AMD<\/span> EPYC<\/span>\u2122 pro\u00adces\u00adsor, code\u00adna\u00admed \u201cVenice,\u201d is the first HPC<\/span> pro\u00adduct in the indus\u00adtry to be taped out and brought up on the TSMC<\/span> advan\u00adced 2nm (N2<\/span>) pro\u00adcess tech\u00adno\u00adlo\u00adgy. This high\u00adlights the strength of AMD<\/span> and TSMC<\/span> semi\u00adcon\u00adduc\u00adtor manu\u00adfac\u00adtu\u00adring part\u00adner\u00adship to co-opti\u00admi\u00adze new design archi\u00adtec\u00adtures with lea\u00adding-edge pro\u00adcess tech\u00adno\u00adlo\u00adgy. It also marks a major step for\u00adward in the exe\u00adcu\u00adti\u00adon of the AMD<\/span> data cen\u00adter CPU<\/span> road\u00admap, with \u201cVenice\u201d on track to launch next year. AMD<\/span> also announ\u00adced the suc\u00adcessful bring up and vali\u00adda\u00adti\u00adon of its 5th<\/sup> Gen AMD<\/span> EPYC<\/span>\u2122 CPU<\/span> pro\u00adducts at TSMC<\/span>\u2019s new fabri\u00adca\u00adti\u00adon faci\u00adli\u00adty in Ari\u00adzo\u00adna, unders\u00adcoring its com\u00admit\u00adment to U.S. manufacturing.
    \n (\u2026)     Wei\u00adter\u00adle\u00adsen \u00bb<\/a><\/p>\n","protected":false},"author":25,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"wp_typography_post_enhancements_disabled":false,"ngg_post_thumbnail":0,"footnotes":""},"categories":[22],"tags":[966,1813,1037,2892],"class_list":["post-68276","post","type-post","status-publish","format-standard","hentry","category-pressemitteilungen","tag-amd","tag-amd-epyc","tag-tsmc","tag-venice","entry"],"share_on_mastodon":{"url":"https:\/\/mastodon.social\/@Planet_3DNow\/114364325111132748","error":""},"_links":{"self":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/68276","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/users\/25"}],"replies":[{"embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/comments?post=68276"}],"version-history":[{"count":2,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/68276\/revisions"}],"predecessor-version":[{"id":68278,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/posts\/68276\/revisions\/68278"}],"wp:attachment":[{"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/media?parent=68276"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/categories?post=68276"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.planet3dnow.de\/cms\/wp-json\/wp\/v2\/tags?post=68276"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}