Anandtech hat eine umfangreiche Dokumentation des Athlon 4 online gestellt, in der praktisch keine Fragen offen bleiben. Hier ein kurzer Auszug:
"The TLB for the L1 cache on the Athlon 4 has received an increase in the number of entries, which increases the hit rate for the Athlon's TLB. The Thunderbird only had a 24-entry L1 TLB compared to the 32-entry L1 TLB on the Pentium III for the instruction cache and a 32-entry TLB for the L1 data cache as opposed to the Pentium III's 72-entry L1 D-cache TLB; Unfortunately AMD did not have the exact number of L1 TLB entries of the Athlon 4. We simply know that they did increase the number. "
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