| Change |
Classification |
Core-logic Impact |
Graphics Card Impact |
| AGP 8x transfer rate for Data and SBA |
Performance |
Required |
Required |
| Parallel terminated, low voltage signaling |
Performance |
Required |
Required |
| Hardware enforced coherency outside the GART range for all transactions |
Feature Change |
Required |
Optional |
| "Long" Transaction Types Removed |
Feature Removal |
Required |
Required |
| No PIPE mode Adresses |
Feature Removal |
Need to support Pipe |
Required |
| High Priority Transaction removed |
Feature Removal |
Required |
Cannot use HP transactions |
| Some changes to ordering rules |
Performance |
Optional |
Required |
| 3.3V AGP signaling |
Feature Removal |
Need to support 3.3V AGP |
Supported in a "Universal AGP 3.0" Implementation |
| Calibration cyble |
Performance |
Required |
Required |
Core-Logic AGP Ressourcen
in PCI-to-PCI bridge |
Feature Enhancement |
Optional |
no Impact |
| Dynamic Bus Inversion |
Performance |
Required |
Required |
| Support for isochronous Transactions |
Feature Addition |
Optional |
Optional |
| Hardware enforced coherency inside GART region selectable on Page basis |
Feature Enhancement |
Optional |
Optional |
| Flow Control Change on Fast Writes |
Feature Enhancement |
No Impact |
Required |
| Multiple AGP Ports support |
Feature Enhancement |
Optional |
No Impact |
| Ability to support multiple page sizes in GART |
Feature Enhancement |
Optional |
No Impact |
| Specified set of AGP 3.0 configuration registers |
Feature Enhancement |
Low |
Low |
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