News Sum­ma­ry:

• AMD has begun pro­duc­tion ramp of its 6th Gen AMD EPYC™ CPUs, code­na­med “Venice,” mar­king a major mile­stone for the AMD and TSMC col­la­bo­ra­ti­on on 2nm technology
• “Venice” is the first HPC pro­duct in the indus­try to achie­ve pro­duc­tion ramp on TSMC advan­ced 2nm technology
• Cri­ti­cal mile­stone achie­ved as agen­tic AI workloads dri­ve demand for acce­le­ra­ted AI infra­struc­tu­re deployments
• AMD con­ti­nues to dri­ve 2nm pro­duct expan­si­on with “Ver­ano” a fol­low on to “Venice” with indus­try lea­ding inte­gra­ti­on of LPDDR for gro­wing memo­ry demand in agen­tic AI workloads

SANTA CLARA, Calif., May 21, 2026 (GLOBE NEWSWIRE) — AMD (NASDAQ: AMD) today announ­ced that its next-gene­ra­ti­on AMD EPYC™ pro­ces­sor, code­na­med “Venice,” is ram­ping pro­duc­tion in Tai­wan on TSMC’s advan­ced 2nm pro­cess tech­no­lo­gy, with future plans to ramp pro­duc­tion at TSMC’s Ari­zo­na fabri­ca­ti­on faci­li­ty. The mile­stone in the exe­cu­ti­on of the AMD data cen­ter CPU road­map demons­tra­tes con­tin­ued pro­gress toward deli­ve­ring the lea­der­ship per­for­mance and ener­gy effi­ci­en­cy requi­red for next-gene­ra­ti­on cloud, enter­pri­se and AI infra­struc­tu­re. “Venice” is the first high-per­for­mance com­pu­ting (HPC) pro­duct in the indus­try to enter pro­duc­tion on TSMC’s advan­ced 2nm pro­cess technology.

“Ram­ping ‘Venice’ on TSMC 2nm pro­cess tech­no­lo­gy marks an important step for­ward in acce­le­ra­ting the next gene­ra­ti­on of AI infra­struc­tu­re,” said Dr. Lisa Su, chair and CEO, AMD. “As AI and agen­tic workloads sca­le rapidly, cus­to­mers need plat­forms that can move from inno­va­ti­on to pro­duc­tion fas­ter. Our deep part­ner­ship with TSMC is hel­ping AMD bring lea­der­ship com­pu­te tech­no­lo­gies to mar­ket with the speed and sca­le requi­red to meet this moment.”

As AI adop­ti­on expands from trai­ning and infe­rence to incre­asing­ly com­plex agen­tic workloads, the CPU is beco­ming even more cri­ti­cal to sca­ling AI infra­struc­tu­re, coor­di­na­ting data move­ment, net­wor­king, sto­rage, secu­ri­ty and sys­tem orchestra­ti­on across the data cen­ter. The ramp of “Venice” comes as AMD con­ti­nues to build momen­tum in the ser­ver mar­ket, reflec­ting gro­wing cus­to­mer demand for EPYC pro­ces­sors to power modern cloud, enter­pri­se, HPC and AI deployments.

The “Venice” ramp in Tai­wan and plans to ramp at TSMC Ari­zo­na reflect AMD’s focus on streng­thening its geo­gra­phi­cal­ly diver­se advan­ced manu­fac­tu­ring foot­print. By pai­ring next-gene­ra­ti­on EPYC pro­ces­sor inno­va­ti­on with advan­ced manu­fac­tu­ring capa­ci­ty across the glo­be, AMD is expan­ding the foun­da­ti­on nee­ded to sup­port cus­to­mers as they deploy and sca­le AI infrastructure.

“We are plea­sed to see AMD con­ti­nue to make strong pro­gress with its next-gene­ra­ti­on EPYC pro­ces­sor on our advan­ced 2nm pro­cess tech­no­lo­gy,” said Dr. C.C. Wei, Chair­man and CEO, TSMC. “Our clo­se col­la­bo­ra­ti­on with AMD reflects the importance of pai­ring lea­der­ship pro­cess tech­no­lo­gy with advan­ced design inno­va­ti­on to enable the next era of high-per­for­mance and AI computing.”

AMD also plans to extend TSMC 2nm pro­cess tech­no­lo­gy across its data cen­ter CPU road­map with “Ver­ano,” a 6th Gen EPYC pro­ces­sor opti­mi­zed for per­for­mance-per-dol­lar-per-watt lea­der­ship. Desi­gned to sup­port cloud and AI com­pu­ting workloads, “Ver­ano” is expec­ted to build on the AMD EPYC plat­form with advan­ced memo­ry inno­va­tions, inclu­ding LPDDR, to deli­ver the CPU per­for­mance, band­width and effi­ci­en­cy requi­red for incre­asing­ly power cons­trai­ned workloads and applications.

AMD and TSMC’s part­ner­ship spans the tech­no­lo­gies nee­ded to sca­le modern data cen­ter com­pu­ting, from TSMC 2nm pro­cess tech­no­lo­gy for next-gene­ra­ti­on CPUs to advan­ced pack­a­ging tech­no­lo­gies, inclu­ding TSMC’s SoIC®-X and CoWoS®-L, used across AMD’s broa­der AI and data cen­ter port­fo­lio. With “Venice” ram­ping on TSMC 2nm, AMD is advan­cing the CPU foun­da­ti­on for AI infra­struc­tu­re while con­ti­nuing to levera­ge TSMC’s pro­cess and pack­a­ging lea­der­ship to deli­ver incre­asing­ly inte­gra­ted com­pu­te plat­forms at scale.

About AMD

AMD (NASDAQ: AMD) dri­ves inno­va­ti­on in high-per­for­mance and AI com­pu­ting to sol­ve the world’s most important chal­lenges. Today, AMD tech­no­lo­gy powers bil­li­ons of expe­ri­en­ces across cloud and AI infra­struc­tu­re, embedded sys­tems, AI PCs and gam­ing. With a broad port­fo­lio of AI-opti­mi­zed CPUs, GPUs, net­wor­king and soft­ware, AMD deli­vers full-stack AI solu­ti­ons that pro­vi­de the per­for­mance and sca­la­bi­li­ty nee­ded for a new era of intel­li­gent com­pu­ting. Learn more at www.amd.com.

Cau­tio­na­ry Statement

This press release con­ta­ins for­ward-loo­king state­ments con­cer­ning Advan­ced Micro Devices, Inc. (AMD) such as the ram­ping of AMD’s 6th Gen AMD EPYC™ CPUs and future plans and expec­ta­ti­ons of its part­ner­ship with TSMC, which are made pur­su­ant to the Safe Har­bor pro­vi­si­ons of the Pri­va­te Secu­ri­ties Liti­ga­ti­on Reform Act of 1995. For­ward-loo­king state­ments are com­mon­ly iden­ti­fied by words such as “would,” “may,” “expects,” “belie­ves,” “plans,” “intends,” “pro­jects” and other terms with simi­lar mea­ning. Inves­tors are cau­tio­ned that the for­ward-loo­king state­ments in this press release are based on cur­rent beliefs, assump­ti­ons and expec­ta­ti­ons, speak only as of the date of this press release and invol­ve risks and uncer­tain­ties that could cau­se actu­al results to dif­fer mate­ri­al­ly from cur­rent expec­ta­ti­ons. Such state­ments are sub­ject to cer­tain known and unknown risks and uncer­tain­ties, many of which are dif­fi­cult to pre­dict and are gene­ral­ly bey­ond AMD’s con­trol, that could cau­se actu­al results and other future events to dif­fer mate­ri­al­ly from tho­se expres­sed in, or impli­ed or pro­jec­ted by, the for­ward-loo­king infor­ma­ti­on and state­ments. Mate­ri­al fac­tors that could cau­se actu­al results to dif­fer mate­ri­al­ly from cur­rent expec­ta­ti­ons include, wit­hout limi­ta­ti­on, the fol­lo­wing: impact of govern­ment actions and regu­la­ti­ons such as export regu­la­ti­ons, import tariffs, trade pro­tec­tion mea­su­res, and licen­sing requi­re­ments; com­pe­ti­ti­ve mar­kets in which AMD’s pro­ducts are sold; the cycli­cal natu­re of the semi­con­duc­tor indus­try; mar­ket con­di­ti­ons of the indus­tries in which AMD pro­ducts are sold; AMD’s abili­ty to intro­du­ce pro­ducts on a time­ly basis with expec­ted fea­tures and per­for­mance levels; loss of a signi­fi­cant cus­to­mer; eco­no­mic and mar­ket uncer­tain­ty; quar­ter­ly and sea­so­nal sales pat­terns; AMD’s abili­ty to ade­qua­te­ly pro­tect its tech­no­lo­gy or other intellec­tu­al pro­per­ty; unfa­vorable cur­ren­cy exch­an­ge rate fluc­tua­tions; abili­ty of third par­ty manu­fac­tu­r­ers to manu­fac­tu­re AMD’s pro­ducts on a time­ly basis in suf­fi­ci­ent quan­ti­ties and using com­pe­ti­ti­ve tech­no­lo­gies; avai­la­bi­li­ty of essen­ti­al equip­ment, mate­ri­als, com­pon­ents (such as memo­ry sup­p­ly), sub­stra­tes or manu­fac­tu­ring pro­ces­ses; abili­ty to achie­ve expec­ted manu­fac­tu­ring yields for AMD’s pro­ducts; AMD’s abili­ty to gene­ra­te reve­nue from its semi-cus­tom SoC pro­ducts; poten­ti­al secu­ri­ty vul­nerabi­li­ties; poten­ti­al secu­ri­ty inci­dents inclu­ding IT outa­ges, data loss, data brea­ches and cyber­at­tacks; uncer­tain­ties invol­ving the orde­ring and ship­ment of AMD’s pro­ducts; AMD’s reli­ance on third-par­ty intellec­tu­al pro­per­ty to design and intro­du­ce new pro­ducts; AMD’s reli­ance on third-par­ty com­pa­nies for design, manu­fac­tu­re and sup­p­ly of mother­boards, soft­ware, memo­ry and other com­pu­ter plat­form com­pon­ents; AMD’s reli­ance on Micro­soft and other soft­ware ven­dors’ sup­port to design and deve­lop soft­ware to run on AMD’s pro­ducts; AMD’s reli­ance on third-par­ty dis­tri­bu­tors and add-in-board part­ners; impact of modi­fi­ca­ti­on or inter­rup­ti­on of AMD’s inter­nal busi­ness pro­ces­ses and infor­ma­ti­on sys­tems; com­pa­ti­bi­li­ty of AMD’s pro­ducts with some or all indus­try-stan­dard soft­ware and hard­ware; cos­ts rela­ted to defec­ti­ve pro­ducts; fail­ure to main­tain an effi­ci­ent sup­p­ly chain as cus­to­mer demand chan­ges; AMD’s abili­ty to rely on third par­ty sup­p­ly-chain logi­stics func­tions; AMD’s abili­ty to effec­tively con­trol sales of its pro­ducts on the gray mar­ket; impact of cli­ma­te chan­ge on AMD’s busi­ness; AMD’s abili­ty to rea­li­ze its defer­red tax assets; poten­ti­al tax lia­bi­li­ties; cur­rent and future claims and liti­ga­ti­on; impact of envi­ron­men­tal laws, con­flict mine­rals rela­ted pro­vi­si­ons and other laws or regu­la­ti­ons; evol­ving expec­ta­ti­ons from govern­ments, inves­tors, cus­to­mers and other stake­hol­ders regar­ding cor­po­ra­te respon­si­bi­li­ty mat­ters; issues rela­ted to the respon­si­ble use of AI; rest­ric­tions impo­sed by agree­ments gover­ning AMD’s notes, the gua­ran­tees of Xilinx’s notes and the revol­ving cre­dit agree­ment; AMD’s abili­ty to satis­fy finan­cial obli­ga­ti­ons under gua­ran­tees, lea­ses and other com­mer­cial com­mit­ments; impact of acqui­si­ti­ons, joint ven­tures and/or invest­ments on AMD’s busi­ness and AMD’s abili­ty to inte­gra­te acqui­red busi­nesses; impact of any impair­ment of the com­bi­ned company’s assets; poli­ti­cal, legal and eco­no­mic risks and natu­ral dis­as­ters; future impairm­ents of tech­no­lo­gy licen­se purcha­ses; AMD’s abili­ty to attract and retain key employees; and AMD’s stock pri­ce vola­ti­li­ty. Inves­tors are urged to review in detail the risks and uncer­tain­ties in AMD’s Secu­ri­ties and Exch­an­ge Com­mis­si­on filings, inclu­ding but not limi­t­ed to AMD’s most recent reports on Forms 10‑K and 10‑Q.