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Rambus Announces Comprehensive PCI Express 5.0 Interface Solution

Verfasst vonpipin

High­lights: 

  • Inte­gra­ted and opti­mi­zed PHY and digi­tal con­trol­ler solu­ti­on enables high-band­width and low-laten­cy con­nec­ti­vi­ty for next-gene­ra­ti­on appli­ca­ti­ons in arti­fi­ci­al intel­li­gence (AI), data cen­ter, high-per­for­mance com­pu­ting (HPC), enter­pri­se and cloud sto­rage, and 400GbE networking
  • PHY sup­ports both PCIe as well Com­pu­te Express Link (CXL) con­nec­ti­vi­ty bet­ween host pro­ces­sor and workload acce­le­ra­tors for hete­ro­ge­nous computing
  • Deli­vers supe­ri­or power, per­for­mance and area on advan­ced 7nm Fin­FET pro­cess node

SUNNYVALE, Calif. – Nov. 12, 2019 – Ram­bus Inc. (NASDAQ: RMBS), a pre­mier sili­con IP and chip pro­vi­der making data fas­ter and safer, today announ­ced it now offers a com­pre­hen­si­ve and opti­mi­zed inter­face solu­ti­on desi­gned for PCI Express (PCIe) 5.0, with back­ward com­pa­ti­bi­li­ty to PCIe 4.0, 3.0 and 2.0. The Ram­bus PCIe 5.0 inter­face solu­ti­on includes both PHY and digi­tal con­trol­ler for easy SoC inte­gra­ti­on and fas­ter time to mar­ket. With the PHY desi­gned for an advan­ced 7nm pro­cess node, the inte­gra­ted solu­ti­on offers best-in-class power, per­for­mance and area thanks to the indus­try-pro­ven engi­nee­ring and signal inte­gri­ty exper­ti­se of Rambus.

“Our high-speed Ser­Des and memo­ry inter­face solu­ti­ons make pos­si­ble ama­zing advance­ments in per­for­mance-inten­si­ve appli­ca­ti­ons in AI, data cen­ter, HPC, sto­rage and net­wor­king,” said Hemant Dhul­la, vice pre­si­dent and gene­ral mana­ger of IP cores at Ram­bus. “Now we’ve added PCIe 5 to our indus­try-lea­ding port­fo­lio of high-speed inter­face solu­ti­ons giving chip makers ano­ther tool to unleash the power of their designs.”

In addi­ti­on to the sta­te-of-the-art PHY, the Ram­bus PCIe 5.0 solu­ti­on includes a high-per­for­mance, digi­tal con­trol­ler core from recent­ly acqui­red Nor­thwest Logic. The Ram­bus PHY and con­trol­ler are offe­red as a ful­ly vali­da­ted and inte­gra­ted solu­ti­on, or they can be licen­sed sepa­ra­te­ly and used with third-par­ty solu­ti­ons. The enti­re solu­ti­on is backed by Ram­bus design, inte­gra­ti­on and sup­port ser­vices for first-time cus­to­mer success.

Bene­fits of Ram­bus PCIe 5.0 Solution

  • Inte­gra­ted and co-vali­da­ted PHY and digi­tal con­trol­ler for com­ple­te inter­face solution
  • Built with Ram­bus’ indus­try-pro­ven design metho­do­lo­gy for long-reach PCIe interfaces
  • 32 GT/s band­width per lane with 128 GB/s band­width in x16 configuration
  • Back­ward com­pa­ti­ble to PCIe 4.0, 3.0 and 2.0
  • PHY Sup­ports Com­pu­te Express Link interconnect
  • Advan­ced mul­ti-tap trans­cei­ver and recei­ver equa­liza­ti­on com­pen­sa­te for more than 36dB of inser­ti­on loss
  • Best-in-class power, per­for­mance and area
  • Sup­ports per­for­mance-inten­si­ve appli­ca­ti­ons inclu­ding AI, data cen­ter, HPC, sto­rage and 400GbE networking

Avai­la­bi­li­ty and Addi­tio­nal Information
The new Ram­bus PCIe 5.0 solu­ti­on is available world­wi­de in an advan­ced 7nm Fin­FET process.

For more infor­ma­ti­on on our com­ple­te fami­ly of Ser­Des solu­ti­ons, plea­se visit rambus.com/serdes.