Rambus Announces Comprehensive PCI Express 5.0 Interface Solution


  • Inte짯gra짯ted and opti짯mi짯zed PHY and digi짯tal con짯trol짯ler solu짯ti짯on enables high-band짯width and low-laten짯cy con짯nec짯ti짯vi짯ty for next-gene짯ra짯ti짯on appli짯ca짯ti짯ons in arti짯fi짯ci짯al intel짯li짯gence (AI), data cen짯ter, high-per짯for짯mance com짯pu짯ting (HPC), enter짯pri짯se and cloud sto짯rage, and 400GbE networking
  • PHY sup짯ports both PCIe as well Com짯pu짯te Express Link (CXL) con짯nec짯ti짯vi짯ty bet짯ween host pro짯ces짯sor and workload acce짯le짯ra짯tors for hete짯ro짯ge짯nous computing
  • Deli짯vers supe짯ri짯or power, per짯for짯mance and area on advan짯ced 7nm Fin짯FET pro짯cess node

SUNNYVALE, Calif.  Nov. 12, 2019  Ram짯bus Inc. (NASDAQRMBS), a pre짯mier sili짯con IP and chip pro짯vi짯der making data fas짯ter and safer, today announ짯ced it now offers a com짯pre짯hen짯si짯ve and opti짯mi짯zed inter짯face solu짯ti짯on desi짯gned for PCI Express (PCIe) 5.0, with back짯ward com짯pa짯ti짯bi짯li짯ty to PCIe 4.0, 3.0 and 2.0. The Ram짯bus PCIe 5.0 inter짯face solu짯ti짯on includes both PHY and digi짯tal con짯trol짯ler for easy SoC inte짯gra짯ti짯on and fas짯ter time to mar짯ket. With the PHY desi짯gned for an advan짯ced 7nm pro짯cess node, the inte짯gra짯ted solu짯ti짯on offers best-in-class power, per짯for짯mance and area thanks to the indus짯try-pro짯ven engi짯nee짯ring and signal inte짯gri짯ty exper짯ti짯se of Rambus.

Our high-speed Ser짯Des and memo짯ry inter짯face solu짯ti짯ons make pos짯si짯ble ama짯zing advance짯ments in per짯for짯mance-inten짯si짯ve appli짯ca짯ti짯ons in AI, data cen짯ter, HPC, sto짯rage and net짯wor짯king, said Hemant Dhul짯la, vice pre짯si짯dent and gene짯ral mana짯ger of IP cores at Ram짯bus. 쏯ow we셶e added PCIe 5 to our indus짯try-lea짯ding port짯fo짯lio of high-speed inter짯face solu짯ti짯ons giving chip makers ano짯ther tool to unleash the power of their designs.

In addi짯ti짯on to the sta짯te-of-the-art PHY, the Ram짯bus PCIe 5.0 solu짯ti짯on includes a high-per짯for짯mance, digi짯tal con짯trol짯ler core from recent짯ly acqui짯red Nor짯thwest Logic. The Ram짯bus PHY and con짯trol짯ler are offe짯red as a ful짯ly vali짯da짯ted and inte짯gra짯ted solu짯ti짯on, or they can be licen짯sed sepa짯ra짯te짯ly and used with third-par짯ty solu짯ti짯ons. The enti짯re solu짯ti짯on is backed by Ram짯bus design, inte짯gra짯ti짯on and sup짯port ser짯vices for first-time cus짯to짯mer success.

Bene짯fits of Ram짯bus PCIe 5.0 Solution

  • Inte짯gra짯ted and co-vali짯da짯ted PHY and digi짯tal con짯trol짯ler for com짯ple짯te inter짯face solution
  • Built with Ram짯bus indus짯try-pro짯ven design metho짯do짯lo짯gy for long-reach PCIe interfaces
  • 32 GT/s band짯width per lane with 128 GB/s band짯width in x16 configuration
  • Back짯ward com짯pa짯ti짯ble to PCIe 4.0, 3.0 and 2.0
  • PHY Sup짯ports Com짯pu짯te Express Link interconnect
  • Advan짯ced mul짯ti-tap trans짯cei짯ver and recei짯ver equa짯liza짯ti짯on com짯pen짯sa짯te for more than 36dB of inser짯ti짯on loss
  • Best-in-class power, per짯for짯mance and area
  • Sup짯ports per짯for짯mance-inten짯si짯ve appli짯ca짯ti짯ons inclu짯ding AI, data cen짯ter, HPC, sto짯rage and 400GbE networking

Avai짯la짯bi짯li짯ty and Addi짯tio짯nal Information
The new Ram짯bus PCIe 5.0 solu짯ti짯on is available world짯wi짯de in an advan짯ced 7nm Fin짯FET process.

For more infor짯ma짯ti짯on on our com짯ple짯te fami짯ly of Ser짯Des solu짯ti짯ons, plea짯se visit rambus.com/serdes.