AMD Introduces World’s Largest FPGA-Based Adaptive SoC for Emulation and Prototyping

 AMD Ver­sal Pre­mi­um VP1902 adap­ti­ve SoC offers 2X the capa­ci­ty of pre­vious-gene­ra­ti­on FPGAs, pro­vi­ding chip­ma­kers with the tools to bring new ASIC and SoC designs to mar­ket fas­ter 

 Col­la­bo­ra­ti­on with EDA lea­ders Cadence, Sie­mens and Syn­op­sys helps ensu­re chip desi­gners have access to sca­lable eco­sys­tem of ful­ly-fea­tured solu­ti­ons 

SANTA CLARA, Calif., June 27, 2023 (GLOBE NEWSWIRE) — AMD (NASDAQ: AMD) today announ­ced the AMD Ver­sal™ Pre­mi­um VP1902 adap­ti­ve sys­tem-on-chip (SoC), the world’s lar­gest1 adap­ti­ve SoC. The VP1902 adap­ti­ve SoC is an emu­la­ti­on-class, chip­let-based device desi­gned to stream­li­ne the veri­fi­ca­ti­on of incre­asing­ly com­plex semi­con­duc­tor designs. Offe­ring 2X2 the capa­ci­ty over the pri­or gene­ra­ti­on, desi­gners can con­fi­dent­ly inno­va­te and vali­da­te appli­ca­ti­on-spe­ci­fic inte­gra­ted cir­cuits (ASICs) and SoC designs to help bring next gene­ra­ti­on tech­no­lo­gies to mar­ket faster.
AI workloads are dri­ving increased com­ple­xi­ty in chip­ma­king, requi­ring next-gene­ra­ti­on solu­ti­ons to deve­lop the chips of tomor­row. FPGA-based emu­la­ti­on and pro­to­ty­p­ing pro­vi­des the hig­hest level of per­for­mance, allo­wing fas­ter sili­con veri­fi­ca­ti­on and enab­ling deve­lo­pers to shift left in the design cycle and begin soft­ware deve­lo­p­ment well befo­re sili­con tape-out. AMD, through Xilinx, brings over 17 years of lea­der­ship and six gene­ra­ti­ons of the industry’s hig­hest capa­ci­ty emu­la­ti­on devices, which have near­ly dou­bled in capa­ci­ty each gene­ra­ti­on3.
“Deli­ve­ring foun­da­tio­nal com­pu­te tech­no­lo­gy to enable our cus­to­mers is a top prio­ri­ty. In emu­la­ti­on and pro­to­ty­p­ing, that means deli­ve­ring the hig­hest capa­ci­ty and per­for­mance pos­si­ble,” said Kirk Saban, cor­po­ra­te vice pre­si­dent, Pro­duct, Soft­ware, & Solu­ti­ons Mar­ke­ting, Adap­ti­ve and Embedded Com­pu­ting Group, AMD. “Chip desi­gners can con­fi­dent­ly emu­la­te and pro­to­ty­pe next-gene­ra­ti­on pro­ducts using our VP1902 adap­ti­ve SoC, acce­le­ra­ting tomorrow’s inno­va­tions in AI, auto­no­mous vehic­les, Indus­try 5.0 and other emer­ging technologies.”

Con­fi­dent­ly Emu­la­te and Pro­to­ty­pe Next-Gene­ra­ti­on Designs
As com­ple­xi­ty grows in ASIC and SoC designs, espe­ci­al­ly with the rapid advance­ment of AI and ML-based chips, exten­si­ve veri­fi­ca­ti­on of both sili­con and soft­ware befo­re tape-out is a must.
The VP1902 deli­vers indus­try lea­ding capa­ci­ty and con­nec­ti­vi­ty, deli­ve­ring 18.5M logic cells for 2X2 hig­her pro­gramma­ble logic den­si­ty and 2X4 aggre­ga­te I/O band­width com­pared to the pre­vious gene­ra­ti­on Vir­tex™ UltraS­ca­le+™ VU19P FPGA.

Ite­ra­te Designs Fast with Unmat­ched Debug Capabilities
Debug is essen­ti­al for pre-sili­con veri­fi­ca­ti­on and con­cur­rent soft­ware deve­lo­p­ment. Fin­ding and addres­sing bugs befo­re tape-out keeps pro­grams on sche­du­le and bud­get. The VP1902 adap­ti­ve SoC lever­a­ges the Ver­sal archi­tec­tu­re, inclu­ding the pro­gramma­ble net­work-on-chip, to pro­vi­de up to 8X5 fas­ter debug­ging com­pared to the pri­or gene­ra­ti­on VU19P FPGA.

Deve­lo­p­ment Tools and Eco­sys­tem Collaborations
The AMD Viv­a­do™ ML design suite pro­vi­des cus­to­mers with a com­pre­hen­si­ve deve­lo­p­ment plat­form to quick­ly design, debug and vali­da­te next-gene­ra­ti­on appli­ca­ti­ons and tech­no­lo­gies and acce­le­ra­te time to mar­ket. New fea­tures that sup­port more effi­ci­ent deve­lo­p­ment on the VP1902 adap­ti­ve SoC include auto­ma­ted design clo­sure assis­tance, inter­ac­ti­ve design tuning, remo­te mul­ti-user real-time debug­ging, and enhan­ced back-end com­pi­la­ti­on, which enables end users to ite­ra­te IC designs faster. 
AMD col­la­bo­ra­tes clo­se­ly with the EDA com­mu­ni­ty to help cus­to­mers turn their inno­va­tions and tech­no­lo­gy visi­on into rea­li­ty. Working clo­se­ly with the top EDA ven­dors, inclu­ding Cadence, Sie­mens and Syn­op­sys helps desi­gners access an eco­sys­tem of ful­ly-fea­tured and sca­lable solutions.
The AMD Ver­sal Pre­mi­um VP1902 adap­ti­ve SoC will begin sam­pling in Q3 to ear­ly access cus­to­mers with pro­duc­tion expec­ted in the first half of 2024.

Sup­port­ing Resources

About AMD
For more than 50 years AMD has dri­ven inno­va­ti­on in high-per­for­mance com­pu­ting, gra­phics, and visua­liza­ti­on tech­no­lo­gies. Bil­li­ons of peo­p­le, lea­ding For­tu­ne 500 busi­nesses, and cut­ting-edge sci­en­ti­fic rese­arch insti­tu­ti­ons around the world rely on AMD tech­no­lo­gy dai­ly to impro­ve how they live, work, and play. AMD employees are focu­sed on buil­ding lea­der­ship high-per­for­mance and adap­ti­ve pro­ducts that push the boun­da­ries of what is pos­si­ble. For more infor­ma­ti­on about how AMD is enab­ling today and inspi­ring tomor­row, visit the AMD (NASDAQ: AMDweb­siteblogLin­ke­dIn, and Twit­ter pages.

AMD, the AMD Arrow logo, Viv­a­do, Ver­sal, Vir­tex, UltraS­ca­le+ and com­bi­na­ti­ons the­reof are trade­marks of Advan­ced Micro Devices, Inc. Other names are for infor­ma­tio­nal pur­po­ses only and may be trade­marks of their respec­ti­ve owners.

1 Based on AMD inter­nal ana­ly­sis in May 2023 with a 6‑input LUT count to compa­re the Ver­sal Pre­mi­um VP1902 device ver­sus the Intel Stra­tix 10 GX 10M FPGA. (VER-002)
Based on AMD inter­nal ana­ly­sis in May 2023, com­pa­ring the num­ber of sys­tem logic cells of the Ver­sal Pre­mi­um VP1902 device ver­sus the Vir­tex UltraS­ca­le+ VU19P device. (VER-001)
Based on AMD inter­nal ana­ly­sis in June 2023, com­pa­ring the num­ber of sys­tem logic cells of the Ver­sal Pre­mi­um VP1902 device ver­sus the Vir­tex 5 LX330T device and cal­cu­la­ting an avera­ge across six gene­ra­ti­ons. (VER-010)
4 Based on AMD Labs test­ing using an A6865 packa­ge to simu­la­te the XPIO data rate per­for­mance of an AMD Ver­sal Pre­mi­um VP1902 device ver­sus the published data rate of an AMD Vir­tex UltraS­ca­le+ VU19P FPGA. Actu­al results will vary. (VER-003)
5 Based on AMD inter­nal ana­ly­sis in May 2023, com­pa­ring the readback/writeback per­for­mance of an AMD Ver­sal adap­ti­ve SoC CFI inter­face ver­sus an AMD Vir­tex UltraS­ca­le+ FPGA ICAP inter­face. Actu­al per­for­mance will vary. (VER-004)