Synopsys Delivers Silicon-Proven HBM2E PHY IP Operating at 3.2 Gbps

Design­Wa­re HBM2E PHY IP in TSMC’s N7 Pro­cess Deli­vers High Through­put for Advan­ced Gra­phics, High-Per­for­mance Com­pu­ting and Net­wor­king SoCs
 

MOUNTAIN VIEW, Calif.Feb. 25, 2020 /PRNews­wire/ –

High­lights:

  • Syn­op­sys’ Design­Wa­re HBM2E IP in TSMC’s N7 pro­cess pro­vi­des up to 409 GBps aggre­ga­te memo­ry band­width with low-power con­sump­ti­on and latency
  • The HBM2E PHY has been veri­fied using TSMC’s CoWoS® tech­no­lo­gy inte­gra­ting the test chip with the IP and HBM2E SDRAMs using 2.5D packaging
  • Syn­op­sys’ sili­con-pro­ven HBM2/2E IP solu­ti­on with har­dening exper­ti­se enables desi­gners to meet uni­que, high-per­for­mance appli­ca­ti­on requirements

Syn­op­sys, Inc. (Nasdaq: SNPS) today announ­ced it has deli­ver­ed sili­con-pro­ven HBM2E PHY IP ope­ra­ting at 3.2 giga­bits per second (Gbps), addres­sing high through­put requi­re­ments of advan­ced gra­phics, high-per­for­mance com­pu­ting and net­wor­king SoCs. Veri­fied on TSMC’s Chip-on-Wafer-on-Sub­stra­te (CoWoS®) advan­ced pack­a­ging tech­no­lo­gy, Syn­op­sys’ Design­Wa­re® HBM2E PHY IP offers a micro-bump array that adhe­res to the JEDEC HBM2E SDRAM stan­dard for the shor­test pos­si­ble 2.5D packa­ge rou­tes and hig­hest signal integrity.

With an aggre­ga­ted band­width of 409 giga­bytes per second, the HBM2E PHY deli­vers the requi­red mas­si­ve com­pu­te per­for­mance of sys­tem-on-chips (SoCs) in advan­ced Fin­FET pro­ces­ses. The HBM2E IP is part of Syn­op­sys’ com­pre­hen­si­ve memo­ry inter­face IP solu­ti­on that includes DDR5/4/3/2 and LPDDR5/4/3/2 IP, which have been vali­da­ted in hundreds of designs and ship­ped in mil­li­ons of SoCs.

As a lea­ding glo­bal semi­con­duc­tor manu­fac­tu­rer, SK hynix makes signi­fi­cant invest­ments in deve­lo­ping robust DRAMs that offer increased capa­ci­ty and pro­ces­sing speed while main­tai­ning strict qua­li­ty con­trol,” said Jun Hyun Chun, seni­or vice pre­si­dent, HBM Pro­duct Cham­pi­on and Head of DRAM Design at SK hynix. “We con­ti­nue to col­la­bo­ra­te with Syn­op­sys to pro­vi­de cus­to­mers with a high-per­for­mance HBM DRAM solu­ti­on that is ful­ly-tes­ted and inter­ope­ra­ble with Syn­op­sys’ Design­Wa­re HBM2E IP, which deli­vers the requi­red capa­ci­ty, through­put and power of com­pu­te-inten­si­ve SoCs in advan­ced processes.” 

TSMC’s long histo­ry of suc­cessful col­la­bo­ra­ti­on with Syn­op­sys has pro­vi­ded our mutu­al cus­to­mers with access to a broad port­fo­lio of high-qua­li­ty Design­Wa­re IP on TSMC’s advan­ced pro­cess tech­no­lo­gies, which they can inte­gra­te into their high-per­for­mance SoCs for a wide ran­ge of appli­ca­ti­ons,” said Suk Lee, seni­or direc­tor of the Design Infra­struc­tu­re Manage­ment Divi­si­on at TSMC. “TSMC’s indus­try-lea­ding N7 pro­cess and CoWoS® pack­a­ging tech­no­lo­gies com­bi­ned with Syn­op­sys’ sili­con-pro­ven Design­Wa­re HBM2E IP allows desi­gners to achie­ve fas­ter sili­con-to-packa­ge manu­fac­tu­ring with impro­ved yield, while mini­mi­zing inte­gra­ti­on risk.”

High-per­for­mance com­pu­ting SoCs are requi­ring signi­fi­cant­ly more memo­ry band­width to mana­ge the mas­si­ve amounts of data trans­fer to sup­port rich gra­phics and machi­ne lear­ning workloads,” said John Koe­ter, seni­or vice pre­si­dent of mar­ke­ting and stra­tegy for IP at Syn­op­sys. “As the lea­ding memo­ry inter­face IP pro­vi­der, Syn­op­sys deli­vers a ran­ge of sili­con-pro­ven Design­Wa­re Memo­ry Inter­face IP solu­ti­ons with lea­ding power, per­for­mance, and area to address the most chal­len­ging through­put requirements.” 

Avai­la­bi­li­ty & Resources

The Syn­op­sys Design­Wa­re HBM2/2E IP is available now.
For more infor­ma­ti­on, visit the Design­Wa­re HBM IP web page.

About Design­Wa­re IP

Syn­op­sys is a lea­ding pro­vi­der of high-qua­li­ty, sili­con-pro­ven IP solu­ti­ons for SoC designs. The broad Design­Wa­re IP port­fo­lio includes logic libra­ri­es, embedded memo­ries, embedded test, ana­log IP, wired and wire­less inter­face IP, secu­ri­ty IP, embedded pro­ces­sors, and sub­sys­tems. To acce­le­ra­te pro­to­ty­p­ing, soft­ware deve­lo­p­ment, and inte­gra­ti­on of IP into SoCs, Syn­op­sys’ IP Acce­le­ra­ted initia­ti­ve offers IP pro­to­ty­p­ing kits, IP soft­ware deve­lo­p­ment kits, and IP sub­sys­tems. Syn­op­sys’ exten­si­ve invest­ment in IP qua­li­ty, com­pre­hen­si­ve tech­ni­cal sup­port, and robust IP deve­lo­p­ment metho­do­lo­gy enable desi­gners to redu­ce inte­gra­ti­on risk and acce­le­ra­te time-to-mar­ket. For more infor­ma­ti­on on Design­Wa­re IP, visit http://www.synopsys.com/designware.

About Syn­op­sys

Syn­op­sys, Inc. (Nasdaq: SNPS) is the Sili­con to Soft­ware part­ner for inno­va­ti­ve com­pa­nies deve­lo­ping the elec­tro­nic pro­ducts and soft­ware appli­ca­ti­ons we rely on every day. As the world’s 15th lar­gest soft­ware com­pa­ny, Syn­op­sys has a long histo­ry of being a glo­bal lea­der in elec­tro­nic design auto­ma­ti­on (EDA) and semi­con­duc­tor IP and is also gro­wing its lea­der­ship in soft­ware secu­ri­ty and qua­li­ty solu­ti­ons. Whe­ther you’­re a sys­tem-on-chip (SoC) desi­gner crea­ting advan­ced semi­con­duc­tors, or a soft­ware deve­lo­per wri­ting appli­ca­ti­ons that requi­re the hig­hest secu­ri­ty and qua­li­ty, Syn­op­sys has the solu­ti­ons nee­ded to deli­ver inno­va­ti­ve, high-qua­li­ty, secu­re pro­ducts. Learn more at www.synopsys.com.

Edi­to­ri­al Contact:
Kel­ly James
Syn­op­sys, Inc.
650–584-8972
kellyj@synopsys.com