Schlagwort: Synopsys
Synopsys Accelerates Multi-Die Designs with Industry’s First Complete HBM3 IP and Verification Solutions
HBM3 IP Solution Delivers Maximum Memory Bandwidth of 921 GB/s for High-Performance Computing, AI, and Graphics SoCs
MOUNTAIN VIEW, Calif., Oct. 7, 2021 /PRNewswire/ –
Highlights of this Announcement:
- The DesignWare HBM3 Controller, PHY, and Verification IP reduces integration risk and maximizes memory performance in 2.5D multi-die systems
- Low-latency HBM3 Controller with flexible configuration options enhance memory bandwidth
- Pre-hardened or configurable HBM3 PHY in 5‑nm process operates at 7200 Mbps for up to 2X the data rate and improves power efficiency by up to 60% compared to HBM2E
- Verification IP and memory models for ZeBu and HAPS offer an end-to-end solution for rapid verification closure from IP to SoC
- Synopsys’ 3DIC Compiler, an integrated multi-die design and analysis platform, provides a comprehensive HBM3 auto-routing solution for rapid and robust design development
Synopsys, Inc. (Nasdaq: SNPS) today announced the industry’s first complete HBM3 IP solution, including controller, PHY, and verification IP for 2.5D multi-die package systems. HBM3 technology helps designers meet essential high-bandwidth and low-power memory requirements for system-on-chip (SoC) designs targeting high-performance computing, AI and graphics applications. Synopsys’ DesignWare® HBM3 Controller and PHY IP, built on silicon-proven HBM2E IP, leverage Synopsys’ interposer expertise to provide a low-risk solution that enables high memory bandwidth at up to 921 GB/s.
(…) Weiterlesen »
Synopsys and TSMC Accelerate 2.5D/3DIC Designs with CoWoS‑S and Integrated Fan-Out Certified Design Flows
MOUNTAIN VIEW, Calif., Aug. 25, 2020 — Synopsys, Inc. announced that Synopsys and TSMC have collaborated to deliver certified design flows for advanced packaging solutions using the Synopsys 3DIC Compiler product for both silicon interposer based Chip-on-Wafer-on-Substrate (CoWoS‑S) and high-density wafer-level RDL-based Integrated Fan-Out (InFO‑R) designs. 3DIC Compiler provides packaging design solutions required by today’s complex multi-die systems for applications like high-performance computing (HPC), automotive and mobile.
“Applications such as AI and 5G networking increasingly require higher levels of integration, lower power consumption, smaller form factors, and faster time to production, and this is driving the demand for advanced-packaging technologies,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “TSMC’s Innovative 3DIC technologies such as CoWoS and InFO enable customer innovation with greater functionality and enhanced system performance at increasingly competitive costs. Our collaboration with Synopsys provides customers with a certified solution for designing with TSMC’s CoWoS and InFO packaging technologies to enable high productivity and faster time to functional silicon.” (…) Weiterlesen »
GLOBALFOUNDRIES Partners with Synopsys, Mentor, and Keysight on Interoperable Process Design Kit (iPDK) Support for 22FDX
OpenAccess-based iPDK provides a choice of design suite tools for developers working on GF’s best-in-class 22FDX platform Santa Clara, Calif., July 21, 2020 – GLOBALFOUNDRIES® (GF®) today announced the release and distribution of OpenAccess iPDK libraries optimized for its 22FDX® (22nm FD-SOI) platform. With its best-in-class performance, power consumption, and broad feature integration capability, GF’s differentiated 22FDX (…) Weiterlesen »
Synopsys Delivers Silicon-Proven HBM2E PHY IP Operating at 3.2 Gbps
DesignWare HBM2E PHY IP in TSMC’s N7 Process Delivers High Throughput for Advanced Graphics, High-Performance Computing and Networking SoCs MOUNTAIN VIEW, Calif., Feb. 25, 2020 /PRNewswire/ – Highlights: Synopsys’ DesignWare HBM2E IP in TSMC’s N7 process provides up to 409 GBps aggregate memory bandwidth with low-power consumption and latency The HBM2E PHY has been verified using TSMC’s CoWoS® technology (…) Weiterlesen »
Synopsys’ Fusion Compiler Adopted by AMD
Synopsys and AMD Collaborate to Optimize Synopsys’ Fusion Compiler for Servers Powered by AMD EPYC Processors MOUNTAIN VIEW, Calif., Feb. 19, 2020 Highlights: AMD deploys Synopsys’ Fusion Compiler RTL-to-GDSII product for the development of its next-generation processor products Unique, single-data-model architecture and unified, full-flow optimization engines deliver superior performance, power and area metrics Synopsys, Inc. (Nasdaq: SNPS) today announced (…) Weiterlesen »