Schlagwort: Synopsys

Synopsys Accelerates Multi-Die Designs with Industry’s First Complete HBM3 IP and Verification Solutions

HBM3 IP Solu­ti­on Deli­vers Maxi­mum Memo­ry Band­width of 921 GB/s for High-Per­for­mance Com­pu­ting, AI, and Gra­phics SoCs

MOUNTAIN VIEW, Calif.Oct. 7, 2021 /PRNews­wire/ –

High­lights of this Announcement:

  • The Design­Wa­re HBM3 Con­trol­ler, PHY, and Veri­fi­ca­ti­on IP redu­ces inte­gra­ti­on risk and maxi­mi­zes memo­ry per­for­mance in 2.5D mul­ti-die systems
  • Low-laten­cy HBM3 Con­trol­ler with fle­xi­ble con­fi­gu­ra­ti­on opti­ons enhan­ce memo­ry bandwidth
  • Pre-har­den­ed or con­fi­gura­ble HBM3 PHY in 5‑nm pro­cess ope­ra­tes at 7200 Mbps for up to 2X the data rate and impro­ves power effi­ci­en­cy by up to 60% com­pa­red to HBM2E
  • Veri­fi­ca­ti­on IP and memo­ry models for ZeBu and HAPS offer an end-to-end solu­ti­on for rapid veri­fi­ca­ti­on clo­sure from IP to SoC
  • Syn­op­sys’ 3DIC Com­pi­ler, an inte­gra­ted mul­ti-die design and ana­ly­sis plat­form, pro­vi­des a com­pre­hen­si­ve HBM3 auto-rou­ting solu­ti­on for rapid and robust design development

Syn­op­sys, Inc. (Nasdaq: SNPS) today announ­ced the industry’s first com­ple­te HBM3 IP solu­ti­on, inclu­ding con­trol­ler, PHY, and veri­fi­ca­ti­on IP for 2.5D mul­ti-die packa­ge sys­tems. HBM3 tech­no­lo­gy hel­ps desi­gners meet essen­ti­al high-band­width and low-power memo­ry requi­re­ments for sys­tem-on-chip (SoC) designs tar­ge­ting high-per­for­mance com­pu­ting, AI and gra­phics app­li­ca­ti­ons. Syn­op­sys’ Design­Wa­re® HBM3 Con­trol­ler and PHY IP, built on sili­con-pro­ven HBM2E IP, leverage Syn­op­sys’ inter­po­ser exper­ti­se to pro­vi­de a low-risk solu­ti­on that enab­les high memo­ry band­width at up to 921 GB/s.
(…) Wei­ter­le­sen »

Synopsys and TSMC Accelerate 2.5D/3DIC Designs with CoWoS‑S and Integrated Fan-Out Certified Design Flows

MOUNTAIN VIEW, Calif., Aug. 25, 2020 — Syn­op­sys, Inc. announ­ced that Syn­op­sys and TSMC have col­la­bo­ra­ted to deli­ver cer­ti­fied design flows for advan­ced pack­a­ging solu­ti­ons using the Syn­op­sys 3DIC Com­pi­ler pro­duct for both sili­con inter­po­ser based Chip-on-Wafer-on-Sub­stra­te (CoWoS‑S) and high-den­si­ty wafer-level RDL-based Inte­gra­ted Fan-Out (InFO‑R) designs. 3DIC Com­pi­ler pro­vi­des pack­a­ging design solu­ti­ons requi­red by today’s com­plex mul­ti-die sys­tems for app­li­ca­ti­ons like high-per­for­mance com­pu­ting (HPC), auto­mo­ti­ve and mobile.

App­li­ca­ti­ons such as AI and 5G net­wor­king incre­a­singly requi­re hig­her levels of inte­gra­ti­on, lower power con­sump­ti­on, smal­ler form fac­tors, and fas­ter time to pro­duc­tion, and this is dri­ving the demand for advan­ced-pack­a­ging tech­no­lo­gies,” said Suk Lee, seni­or direc­tor of the Design Infra­st­ruc­tu­re Manage­ment Divi­si­on at TSMC. “TSMC’s Inno­va­ti­ve 3DIC tech­no­lo­gies such as CoWoS and InFO enab­le cus­to­mer inno­va­ti­on with grea­ter func­tio­n­a­li­ty and enhan­ced sys­tem per­for­mance at incre­a­singly com­pe­ti­ti­ve cos­ts. Our col­la­bo­ra­ti­on with Syn­op­sys pro­vi­des cus­to­mers with a cer­ti­fied solu­ti­on for designing with TSMC’s CoWoS and InFO pack­a­ging tech­no­lo­gies to enab­le high pro­duc­ti­vi­ty and fas­ter time to func­tio­n­al sili­con.” (…) Wei­ter­le­sen »

GLOBALFOUNDRIES Partners with Synopsys, Mentor, and Keysight on Interoperable Process Design Kit (iPDK) Support for 22FDX

Ope­n­Ac­cess-based iPDK pro­vi­des a choice of design suite tools for deve­lo­pers working on GF’s best-in-class 22FDX plat­form San­ta Cla­ra, Calif., July 21, 2020 – GLOBALFOUNDRIES® (GF®) today announ­ced the release and dis­tri­bu­ti­on of Ope­n­Ac­cess iPDK libra­ries opti­mi­zed for its 22FDX® (22nm FD-SOI) plat­form. With its best-in-class per­for­mance, power con­sump­ti­on, and broad fea­ture inte­gra­ti­on capa­bi­li­ty, GF’s dif­fe­ren­tia­ted 22FDX (…) Wei­ter­le­sen »

Synopsys Delivers Silicon-Proven HBM2E PHY IP Operating at 3.2 Gbps

Design­Wa­re HBM2E PHY IP in TSMC’s N7 Pro­cess Deli­vers High Through­put for Advan­ced Gra­phics, High-Per­­for­­mance Com­pu­ting and Net­wor­king SoCs   MOUNTAIN VIEW, Calif., Feb. 25, 2020 /PRNews­wire/ – High­lights: Syn­op­sys’ Design­Wa­re HBM2E IP in TSMC’s N7 pro­cess pro­vi­des up to 409 GBps aggre­ga­te memo­ry band­width with low-power con­sump­ti­on and laten­cy The HBM2E PHY has been veri­fied using TSMC’s CoWoS® tech­no­lo­gy (…) Wei­ter­le­sen »

Synopsys’ Fusion Compiler Adopted by AMD

Syn­op­sys and AMD Col­la­bo­ra­te to Opti­mi­ze Syn­op­sys’ Fusi­on Com­pi­ler for Ser­vers Powe­red by AMD EPYC Pro­ces­sors   MOUNTAIN VIEW, Calif., Feb. 19, 2020 High­lights: AMD deploys Syn­op­sys’ Fusi­on Com­pi­ler RTL-to-GDSII pro­duct for the deve­lo­p­ment of its next-gene­r­a­­ti­on pro­ces­sor pro­ducts Uni­que, sin­g­le-data-model archi­tec­tu­re and uni­fied, full-flow opti­miz­a­ti­on engi­nes deli­ver supe­ri­or per­for­mance, power and area metrics Syn­op­sys, Inc. (Nasdaq: SNPS) today announ­ced (…) Wei­ter­le­sen »

Durch die weitere Nutzung der Seite stimmst du der Verwendung von Cookies zu. Weitere Informationen

Die Cookie-Einstellungen auf dieser Website sind auf "Cookies zulassen" eingestellt, um das beste Surferlebnis zu ermöglichen. Wenn du diese Website ohne Änderung der Cookie-Einstellungen verwendest oder auf "Akzeptieren" klickst, erklärst du dich damit einverstanden.

Schließen