HBM3 IP Solu­ti­on Deli­vers Maxi­mum Memo­ry Band­width of 921 GB/s for High-Per­for­mance Com­pu­ting, AI, and Gra­phics SoCs

MOUNTAIN VIEW, Calif., Oct. 7, 2021 /PRNews­wire/ –

High­lights of this Announcement:

• The Design­Wa­re HBM3 Con­trol­ler, PHY, and Veri­fi­ca­ti­on IP redu­ces inte­gra­ti­on risk and maxi­mi­zes memo­ry per­for­mance in 2.5D mul­ti-die systems
• Low-laten­cy HBM3 Con­trol­ler with fle­xi­ble con­fi­gu­ra­ti­on opti­ons enhan­ce memo­ry bandwidth
• Pre-har­den­ed or con­fi­gura­ble HBM3 PHY in 5‑nm pro­cess ope­ra­tes at 7200 Mbps for up to 2X the data rate and impro­ves power effi­ci­en­cy by up to 60% com­pared to HBM2E
• Veri­fi­ca­ti­on IP and memo­ry models for ZeBu and HAPS offer an end-to-end solu­ti­on for rapid veri­fi­ca­ti­on clo­sure from IP to SoC
• Syn­op­sys’ 3DIC Com­pi­ler, an inte­gra­ted mul­ti-die design and ana­ly­sis plat­form, pro­vi­des a com­pre­hen­si­ve HBM3 auto-rou­ting solu­ti­on for rapid and robust design development

Syn­op­sys, Inc. (Nasdaq: SNPS) today announ­ced the industry’s first com­ple­te HBM3 IP solu­ti­on, inclu­ding con­trol­ler, PHY, and veri­fi­ca­ti­on IP for 2.5D mul­ti-die packa­ge sys­tems. HBM3 tech­no­lo­gy helps desi­gners meet essen­ti­al high-band­width and low-power memo­ry requi­re­ments for sys­tem-on-chip (SoC) designs tar­ge­ting high-per­for­mance com­pu­ting, AI and gra­phics appli­ca­ti­ons. Syn­op­sys’ Design­Wa­re® HBM3 Con­trol­ler and PHY IP, built on sili­con-pro­ven HBM2E IP, levera­ge Syn­op­sys’ inter­po­ser exper­ti­se to pro­vi­de a low-risk solu­ti­on that enables high memo­ry band­width at up to 921 GB/s.
(…) Wei­ter­le­sen »