MOUNTAIN VIEW, Calif., Aug. 25, 2020 — Syn­op­sys, Inc. announ­ced that Syn­op­sys and TSMC have col­la­bo­ra­ted to deli­ver cer­ti­fied design flows for advan­ced pack­a­ging solu­ti­ons using the Syn­op­sys 3DIC Com­pi­ler pro­duct for both sili­con inter­po­ser based Chip-on-Wafer-on-Sub­stra­te (CoWoS‑S) and high-den­si­ty wafer-level RDL-based Inte­gra­ted Fan-Out (InFO‑R) designs. 3DIC Com­pi­ler pro­vi­des pack­a­ging design solu­ti­ons requi­red by today’s com­plex mul­ti-die sys­tems for appli­ca­ti­ons like high-per­for­mance com­pu­ting (HPC), auto­mo­ti­ve and mobile.

“Appli­ca­ti­ons such as AI and 5G net­wor­king incre­asing­ly requi­re hig­her levels of inte­gra­ti­on, lower power con­sump­ti­on, smal­ler form fac­tors, and fas­ter time to pro­duc­tion, and this is dri­ving the demand for advan­ced-pack­a­ging tech­no­lo­gies,” said Suk Lee, seni­or direc­tor of the Design Infra­struc­tu­re Manage­ment Divi­si­on at TSMC. “TSMC’s Inno­va­ti­ve 3DIC tech­no­lo­gies such as CoWoS and InFO enable cus­to­mer inno­va­ti­on with grea­ter func­tion­a­li­ty and enhan­ced sys­tem per­for­mance at incre­asing­ly com­pe­ti­ti­ve cos­ts. Our col­la­bo­ra­ti­on with Syn­op­sys pro­vi­des cus­to­mers with a cer­ti­fied solu­ti­on for desig­ning with TSMC’s CoWoS and InFO pack­a­ging tech­no­lo­gies to enable high pro­duc­ti­vi­ty and fas­ter time to func­tion­al sili­con.” (…) Wei­ter­le­sen »