Arm and TSMC Demonstrate Industry‚Äôs First 7nm Arm-based CoWoS¬ģ Chiplets for High-Performance Computing

Hsin¬≠chu, Tai¬≠wan R.O.C., Sep¬≠tem¬≠ber 26, 2019 ‚ÄĒ Arm and TSMC, the High-Per¬≠for¬≠mance Com¬≠pu¬≠ting (HPC) indus¬≠try lea¬≠ders, today announ¬≠ced an indus¬≠try-first 7nm sili¬≠con-pro¬≠ven chip¬≠let sys¬≠tem based on mul¬≠ti¬≠ple Arm¬ģ cores and lever¬≠aging TSMC‚Äôs Chip-on-Wafer-on-Sub¬≠stra¬≠te (CoWoS¬ģ) advan¬≠ced pack¬≠a¬≠ging solu¬≠ti¬≠on. This sin¬≠gle pro¬≠of-of-con¬≠cept chip¬≠let sys¬≠tem suc¬≠cessful¬≠ly demons¬≠tra¬≠tes the key tech¬≠no¬≠lo¬≠gies for buil¬≠ding an HPC Sys¬≠tem-On-Chip (SoC) with Arm-based cores ope¬≠ra¬≠ting at 4GHz in a 7nm Fin¬≠FET pro¬≠cess. The chip¬≠let sys¬≠tem also demons¬≠tra¬≠tes for SoC desi¬≠gners an on-die, bi-direc¬≠tion¬≠al inter¬≠con¬≠nect mesh bus ope¬≠ra¬≠ting at 4GHz, and a chip¬≠let design metho¬≠do¬≠lo¬≠gy con¬≠nec¬≠ted by an 8Gb/s inter-chip¬≠let inter¬≠con¬≠nect over a TSMC CoWoS interposer.

Rather than the tra­di­tio­nal SoC approach of com­bi­ning every sys­tem com­po­nent onto a sin­gle die, chip­let designs are opti­mi­zed for modern HPC pro­ces­sors which par­ti­ti­on lar­ge mul­ti-core designs into smal­ler chip­sets. This effi­ci­ent approach enables func­tions to be split into smal­ler, sepa­ra­te dies which pro­vi­de for the fle­xi­bi­li­ty of pro­du­cing each chip­let on dif­fe­rent pro­cess tech­no­lo­gies, as well as deli­ve­ring bet­ter yields and over­all cost effec­ti­ve­ness. And to ensu­re the hig­hest levels of per­for­mance, chip­lets must com­mu­ni­ca­te with each other through den­se, high-speed, high-band­width con­nec­tions. To address this chall­enge, this chip­let sys­tem fea­tures a uni­que Low-vol­ta­ge-IN-Packa­ge-INter­CON­nect (LIPINCONTM) deve­lo­ped by TSMC which has rea­ched data rates of 8Gb/s per pin with excel­lent power effi­ci­en­cy results.

Chip­let Sys­tem Details
The chip¬≠let sys¬≠tem is com¬≠pri¬≠sed of a dual-chip¬≠let CoWoS imple¬≠men¬≠ted in 7nm, with each chip¬≠let con¬≠tai¬≠ning four Arm Cortex¬ģ-A72 pro¬≠ces¬≠sors and an on-die inter¬≠con¬≠nect mesh bus. The die-to-die inter-chip¬≠let con¬≠nec¬≠tion fea¬≠tures sca¬≠lable 0.56pJ/bit (pico-Joules per bit) power effi¬≠ci¬≠en¬≠cy, 1.6Tb/s/mm2 (tera¬≠bits per second per squa¬≠re mil¬≠li¬≠me¬≠ter) band¬≠width den¬≠si¬≠ty, and 0.3V LIPINCON low-vol¬≠ta¬≠ge inter¬≠face achie¬≠ving 8GT/s (Giga Tran¬≠sac¬≠tions per second) and 320GB/s band¬≠width. The chip¬≠let sys¬≠tem was taped out in Decem¬≠ber 2018, and pro¬≠du¬≠ced in April 2019.

‚ÄúThis latest pro¬≠of-of-con¬≠cept with our long¬≠time part¬≠ner TSMC is an excel¬≠lent foun¬≠da¬≠ti¬≠on for future pro¬≠duc¬≠tion-rea¬≠dy infra¬≠struc¬≠tu¬≠re SoC solu¬≠ti¬≠ons which will inte¬≠gra¬≠te TSMC‚Äôs inno¬≠va¬≠ti¬≠ve advan¬≠ced pack¬≠a¬≠ging tech¬≠no¬≠lo¬≠gy with the unmat¬≠ched fle¬≠xi¬≠bi¬≠li¬≠ty and sca¬≠la¬≠bi¬≠li¬≠ty of the Arm archi¬≠tec¬≠tu¬≠re,‚ÄĚ said Drew Hen¬≠ry, Seni¬≠or Vice Pre¬≠si¬≠dent and Gene¬≠ral Mana¬≠ger of Arm‚Äôs Infra¬≠struc¬≠tu¬≠re Line of Business.

‚ÄúThis demons¬≠tra¬≠ti¬≠on chip is an excel¬≠lent show¬≠ca¬≠se of the sys¬≠tem inte¬≠gra¬≠ti¬≠on capa¬≠bi¬≠li¬≠ties we offer to our cus¬≠to¬≠mers,‚ÄĚ said Dr. Cliff Hou, Vice Pre¬≠si¬≠dent of Tech¬≠no¬≠lo¬≠gy Deve¬≠lo¬≠p¬≠ment for TSMC. ‚ÄúTSMC‚Äôs CoWoS advan¬≠ced pack¬≠a¬≠ging tech¬≠no¬≠lo¬≠gy and LIPINCON inter-chip¬≠let inter¬≠face enable cus¬≠to¬≠mers to par¬≠ti¬≠ti¬≠on lar¬≠ge mul¬≠ti-core designs into smal¬≠ler chip¬≠lets that deli¬≠ver bet¬≠ter yield and bet¬≠ter eco¬≠no¬≠mics. This Arm and TSMC col¬≠la¬≠bo¬≠ra¬≠ti¬≠on fur¬≠ther unleas¬≠hes our cus¬≠to¬≠mers‚Äô inno¬≠va¬≠tions in high-per¬≠for¬≠mance SoC design for cloud-to-edge infra¬≠struc¬≠tu¬≠re applications.‚ÄĚ

Fig. 1: Dual Chip­let Floorplan