AGESA 1.0.0.6 mit Verbesserungen bei DRAM, Virtualisierung und Flexibilität

In sei­nem Blog hat AMD einen Aus­blick auf das AGE­SA-Update 1.0.0.6 gewährt. AGESA steht für AMD Gene­ric Encap­su­la­ted Sys­tem Archi­tec­tu­re und bil­det das Grund­ge­rüst zur Initia­li­sie­rung von AMD-Pro­zes­so­ren in der Pha­se des Power-On-Self-Test (POST) nach dem Ein­schal­ten des Sys­tems. Dar­auf basie­rend ent­wi­ckeln die Main­board-Her­stel­ler ihre Firm­ware (ali­as BIOS ali­as UEFI).

Wie bereits in einem frü­he­ren Blog­bei­trag ver­ra­ten, will AMD mit dem Update 1.0.0.6 die hohen DRAM-Over­clo­cking-Fre­quen­zen ange­hen. Mit Over­clo­cking meint AMD alles über DDR4-2667, der höchs­ten offi­zi­ell für Ryzen frei­ge­ge­be­nen Spei­cher­takt­ra­te. So sol­len künf­tig auch Fre­quen­zen über 3200 MHz ein­stell­bar und vor allem sta­bil nutz­bar sein, denn dass Ryzen eine zicki­ge Diva in Sachen Spei­cher­kom­pa­ti­bi­li­tät sein kann, haben wir ja schon mehr­fach the­ma­ti­siert.

Doch das AGE­SA-Update 1.0.0.6 soll noch wei­te­re Fea­tures frei­schal­ten. So soll es mit IOMMU Groups mög­lich sein, Vir­tu­el­len Maschi­nen ein­zel­ne Gra­fik­kar­ten zuzu­wei­sen:

This capa­bi­li­ty is espe­ci­al­ly use­ful for users that want 3D-acce­le­ra­ted gra­phics insi­de a vir­tu­al machi­ne. With ACS sup­port, it is pos­si­ble to split a 2‑GPU sys­tem such that a host Linux® OS and a Win­dows VM both have a dedi­ca­ted gra­phics cards. The vir­tu­al machi­ne can access all the capa­bi­li­ties of the dedi­ca­ted GPU, and run games insi­de the vir­tu­al machi­ne at near-nati­ve per­for­mance.

Abge­se­hen davon ver­spricht AMD 26 neue Fea­tures, dar­un­ter end­lich die manu­el­le Kon­fi­gu­rier­bar­keit der DRAM Com­mand Rate.

Para­me­ter Func­tion Values
tWTR_S Wri­te to read delay (short), or the time bet­ween a wri­te tran­sac­tion and read com­mand on a dif­fe­rent bank group. Inte­ger values (cycles)
tWTR_L Wri­te to read delay (long), or the time bet­ween a wri­te tran­sac­tion and read com­mand on the same bank group. Inte­ger values (cycles)
tWR Wri­te reco­very time, or the time that must elap­se bet­ween a valid wri­te ope­ra­ti­on and the prech­ar­ging of ano­t­her bank. Hig­her values are often bene­fi­ci­al for sta­bi­li­ty, and values < 8 can quick­ly cor­rupt data stored in RAM. Inte­ger values (ns)
tWR Wri­te reco­very time, or the time that must elap­se bet­ween a valid wri­te ope­ra­ti­on and the prech­ar­ging of ano­t­her bank. Hig­her values are often bet­ter for sta­bi­li­ty. Inte­ger values (ns)
tWCL/tWL/tCWL CAS Wri­te Laten­cy, or the amount of time it takes to wri­te to the open memo­ry bank. WCL is gene­ral­ly con­fi­gu­red equal to CAS or CAS‑1. This can be a signi­fi­cant timing for sta­bi­li­ty, and lower values often pro­ve bet­ter. Inte­ger values (cycles)
tRTP Read to prech­ar­ge time, or the num­ber of clock cycles bet­ween a READ com­mand to a row and a prech­ar­ge com­mand to the same rank. Inte­ger values (cycles)
tRRD_S Activa­te to activa­te delay (short), or the num­ber of clock cycles bet­ween activa­te com­mands in a dif­fe­rent bank group. Inte­ger values (cycles)
tRRD_L Activa­te to activa­te delay (long), or the num­ber of clock cycles bet­ween activa­te com­mands in the same bank group. Inte­ger values (cycles)
tRFC4 Refresh cycle time for quad fre­quen­cy (4x) mode. This is typi­cal­ly a timing auto­ma­ti­cal­ly deri­ved from other values. Inte­ger values (cycles)
tRFC2 Refresh cycle time for dou­ble fre­quen­cy (2x) mode.  This is typi­cal­ly a timing auto­ma­ti­cal­ly deri­ved from other values. Inte­ger values (cycles)
tRFC Refresh cycle time, or the time it takes for the memo­ry to read and re-wri­te infor­ma­ti­on to the same DRAM cell for the pur­po­ses of pre­ser­ving infor­ma­ti­on. This is typi­cal­ly a timing auto­ma­ti­cal­ly deri­ved from other values. Inte­ger values (cycles)
tRD­WR / tWRRD Read-to-wri­te and wri­te-to-read laten­cy, or the time that must elap­se bet­ween issuing sequen­ti­al read/write or write/read com­mands. Inte­ger values (cycles)
tRDRD / tWR­WR Read-to-read and wri­te-to-wri­te laten­cy, or the time bet­ween sequen­ti­al read or wri­te requests (e.g. DIMM-to-DIMM, or across ranks). Lower values can signi­fi­cant­ly impro­ve DRAM through­put, but high memo­ry clocks often demand rela­xed timings. Inte­ger values (cycles)
tRC Row cycle time, or the num­ber of clock cycles requi­red for a memo­ry row to com­ple­te a full ope­ra­tio­nal cycle. Lower values can nota­b­ly impro­ve per­for­mance, but should not be set lower than tRP+tRAS for sta­bi­li­ty rea­sons. Inte­ger values (cycles)
tMAW Maxi­mum activa­ti­on win­dow, or the maxi­mum num­ber of times a DRAM row can be activa­ted befo­re adja­cent memo­ry rows must be refres­hed to pre­ser­ve data. Inte­ger values (cycles)
tMAC Maxi­mum activa­te count, or the num­ber of times a row is activa­ted by the sys­tem befo­re adja­cent row refresh. Must be equal to or less than tMAW. Inte­ger values (cycles)
tFAW Four activa­ti­on win­dow, or the time that must elap­se befo­re new memo­ry banks can be activa­ted after four ACTIVATE com­mands have been issued. Con­fi­gu­red to a min­umum 4x tRRD_S, but values >8x tRRD_S are often used for sta­bi­li­ty. Inte­ger values (ns)
Rtt Con­trols the per­for­mance of DRAM inter­nal ter­mi­na­ti­on resis­tors during nomi­nal, wri­te, and park sta­tes. Nom(inal), WR(ite), and Park inte­gers (ohms)
Pro­cODT (CPU on-die ter­mi­na­ti­on) A resis­tan­ce value, in ohms, that deter­mi­nes how a com­ple­ted memo­ry signal is ter­mi­na­ted. Hig­her values can help sta­bi­li­ze hig­her data rates. Values in the ran­ge of 60–96 can pro­ve hel­pful. Inte­ger values (ohms)
Memo­ry clocks Added divi­ders for memo­ry clocks up to DDR4-4000 wit­hout ref­clk adjust­ment. Plea­se note that values grea­ter than DDR4-2667 is over­clo­cking. Your mileage may vary (as noted by our big over­clo­cking wart­ning at the end of this blog). 133.33MT/s inter­vals (2667, 2933, 3067, 3200, 3333, 3466, 3600, 3733, 3866, 4000)
Gear­down Mode Allows the DRAM device to run off its intern­al­ly-gene­ra­ted ½ rate clock for latching on the com­mand or address buses. ON is the default for speeds grea­ter than DDR4-2667, howe­ver the bene­fit of ON vs. OFF will vary from memo­ry kit to memo­ry kit. Enab­ling Gear­down Mode will over­ri­de your cur­rent com­mand rate. On/Off
DRAM Power Down Can modest­ly save sys­tem power, at the expen­se of hig­her DRAM laten­cy, by put­ting DRAM into a quie­scent sta­te after a peri­od of inac­tivi­ty. On/Off
Com­mand rate (CR) The amount of time, in cycles, bet­ween when a DRAM chip is selec­ted and a com­mand is exe­cu­t­ed. 2T CR can be very bene­fi­ci­al for sta­bi­li­ty with high memo­ry clocks, or for 4‑DIMM con­fi­gu­ra­ti­ons. 2T, 1T
CLDO_VDDP Vol­ta­ge for the DDR4 PHY on the SoC. Some­what coun­ter­in­tui­tively, lowe­ring VDDP can often be more bene­fi­ci­al for sta­bi­li­ty than rai­sing CLDO_VDDP. Advan­ced over­clo­ckers should also know that alte­ring CLDO_VDDP can move or resol­ve memo­ry holes. Small chan­ges to VDDP can have a big effect, and VDDP should not be set to a value grea­ter than VDIMM‑0.1V. A cold reboot is requi­red if you alter this vol­ta­ge.

 

Sideno­te: pre‑1.0.0.6 BIO­Ses may also have an ent­ry labe­led “VDDP” that alters the exter­nal vol­ta­ge level sent to the CPU VDDP pins. This is not the same para­me­ter as CLDO_VDDP in AGESA 1.0.0.6.

Inte­ger values