AGESA 1.0.0.6 mit Verbesserungen bei DRAM, Virtualisierung und Flexibilit채t

In sei짯nem Blog hat AMD einen Aus짯blick auf das AGE짯SA-Update 1.0.0.6 gew채hrt. AGESA steht f체r AMD Gene짯ric Encap짯su짯la짯ted Sys짯tem Archi짯tec짯tu짯re und bil짯det das Grund짯ge짯r체st zur Initia짯li짯sie짯rung von AMD-Pro짯zes짯so짯ren in der Pha짯se des Power-On-Self-Test (POST) nach dem Ein짯schal짯ten des Sys짯tems. Dar짯auf basie짯rend ent짯wi짯ckeln die Main짯board-Her짯stel짯ler ihre Firm짯ware (ali짯as BIOS ali짯as UEFI).

Wie bereits in einem fr체짯he짯ren Blog짯bei짯trag ver짯ra짯ten, will AMD mit dem Update 1.0.0.6 die hohen DRAM-Over짯clo짯cking-Fre짯quen짯zen ange짯hen. Mit Over짯clo짯cking meint AMD alles 체ber DDR4-2667, der h철chs짯ten offi짯zi짯ell f체r Ryzen frei짯ge짯ge짯be짯nen Spei짯cher짯takt짯ra짯te. So sol짯len k체nf짯tig auch Fre짯quen짯zen 체ber 3200 MHz ein짯stell짯bar und vor allem sta짯bil nutz짯bar sein, denn dass Ryzen eine zicki짯ge Diva in Sachen Spei짯cher짯kom짯pa짯ti짯bi짯li짯t채t sein kann, haben wir ja schon mehr짯fach the짯ma짯ti짯siert.

Doch das AGE짯SA-Update 1.0.0.6 soll noch wei짯te짯re Fea짯tures frei짯schal짯ten. So soll es mit IOMMU Groups m철g짯lich sein, Vir짯tu짯el짯len Maschi짯nen ein짯zel짯ne Gra짯fik짯kar짯ten zuzuweisen:

This capa짯bi짯li짯ty is espe짯ci짯al짯ly useful for users that want 3D-acce짯le짯ra짯ted gra짯phics insi짯de a vir짯tu짯al machi짯ne. With ACS sup짯port, it is pos짯si짯ble to split a 2GPU sys짯tem such that a host Linux짰 OS and a Win짯dows VM both have a dedi짯ca짯ted gra짯phics cards. The vir짯tu짯al machi짯ne can access all the capa짯bi짯li짯ties of the dedi짯ca짯ted GPU, and run games insi짯de the vir짯tu짯al machi짯ne at near-nati짯ve performance.

Abge짯se짯hen davon ver짯spricht AMD 26 neue Fea짯tures, dar짯un짯ter end짯lich die manu짯el짯le Kon짯fi짯gu짯rier짯bar짯keit der DRAM Com짯mand Rate.

Para짯me짯ter Func짯tion Values
tWTR_S Wri짯te to read delay (short), or the time bet짯ween a wri짯te tran짯sac짯tion and read com짯mand on a dif짯fe짯rent bank group. Inte짯ger values (cycles)
tWTR_L Wri짯te to read delay (long), or the time bet짯ween a wri짯te tran짯sac짯tion and read com짯mand on the same bank group. Inte짯ger values (cycles)
tWR Wri짯te reco짯very time, or the time that must elap짯se bet짯ween a valid wri짯te ope짯ra짯ti짯on and the prech짯ar짯ging of ano짯ther bank. Hig짯her values are often bene짯fi짯ci짯al for sta짯bi짯li짯ty, and values < 8 can quick짯ly cor짯rupt data stored in RAM. Inte짯ger values (ns)
tWR Wri짯te reco짯very time, or the time that must elap짯se bet짯ween a valid wri짯te ope짯ra짯ti짯on and the prech짯ar짯ging of ano짯ther bank. Hig짯her values are often bet짯ter for stability. Inte짯ger values (ns)
tWCL/tWL/tCWL CAS Wri짯te Laten짯cy, or the amount of time it takes to wri짯te to the open memo짯ry bank. WCL is gene짯ral짯ly con짯fi짯gu짯red equal to CAS or CAS1. This can be a signi짯fi짯cant timing for sta짯bi짯li짯ty, and lower values often pro짯ve better. Inte짯ger values (cycles)
tRTP Read to prech짯ar짯ge time, or the num짯ber of clock cycles bet짯ween a READ com짯mand to a row and a prech짯ar짯ge com짯mand to the same rank. Inte짯ger values (cycles)
tRRD_S Acti짯va짯te to acti짯va짯te delay (short), or the num짯ber of clock cycles bet짯ween acti짯va짯te com짯mands in a dif짯fe짯rent bank group. Inte짯ger values (cycles)
tRRD_L Acti짯va짯te to acti짯va짯te delay (long), or the num짯ber of clock cycles bet짯ween acti짯va짯te com짯mands in the same bank group. Inte짯ger values (cycles)
tRFC4 Refresh cycle time for quad fre짯quen짯cy (4x) mode. This is typi짯cal짯ly a timing auto짯ma짯ti짯cal짯ly deri짯ved from other values. Inte짯ger values (cycles)
tRFC2 Refresh cycle time for dou짯ble fre짯quen짯cy (2x) mode.  This is typi짯cal짯ly a timing auto짯ma짯ti짯cal짯ly deri짯ved from other values. Inte짯ger values (cycles)
tRFC Refresh cycle time, or the time it takes for the memo짯ry to read and re-wri짯te infor짯ma짯ti짯on to the same DRAM cell for the pur짯po짯ses of pre짯ser짯ving infor짯ma짯ti짯on. This is typi짯cal짯ly a timing auto짯ma짯ti짯cal짯ly deri짯ved from other values. Inte짯ger values (cycles)
tRD짯WR / tWRRD Read-to-wri짯te and wri짯te-to-read laten짯cy, or the time that must elap짯se bet짯ween issuing sequen짯ti짯al read/write or write/read commands. Inte짯ger values (cycles)
tRDRD / tWRWR Read-to-read and wri짯te-to-wri짯te laten짯cy, or the time bet짯ween sequen짯ti짯al read or wri짯te requests (e.g. DIMM-to-DIMM, or across ranks). Lower values can signi짯fi짯cant짯ly impro짯ve DRAM through짯put, but high memo짯ry clocks often demand rela짯xed timings. Inte짯ger values (cycles)
tRC Row cycle time, or the num짯ber of clock cycles requi짯red for a memo짯ry row to com짯ple짯te a full ope짯ra짯tio짯nal cycle. Lower values can nota짯b짯ly impro짯ve per짯for짯mance, but should not be set lower than tRP+tRAS for sta짯bi짯li짯ty reasons. Inte짯ger values (cycles)
tMAW Maxi짯mum acti짯va짯ti짯on win짯dow, or the maxi짯mum num짯ber of times a DRAM row can be acti짯va짯ted befo짯re adja짯cent memo짯ry rows must be refres짯hed to pre짯ser짯ve data. Inte짯ger values (cycles)
tMAC Maxi짯mum acti짯va짯te count, or the num짯ber of times a row is acti짯va짯ted by the sys짯tem befo짯re adja짯cent row refresh. Must be equal to or less than tMAW. Inte짯ger values (cycles)
tFAW Four acti짯va짯ti짯on win짯dow, or the time that must elap짯se befo짯re new memo짯ry banks can be acti짯va짯ted after four ACTIVATE com짯mands have been issued. Con짯fi짯gu짯red to a min짯u짯mum 4x tRRD_S, but values >8x tRRD_S are often used for stability. Inte짯ger values (ns)
Rtt Con짯trols the per짯for짯mance of DRAM inter짯nal ter짯mi짯na짯ti짯on resis짯tors during nomi짯nal, wri짯te, and park states. Nom(inal), WR(ite), and Park inte짯gers (ohms)
Pro짯cODT (CPU on-die termination) A resis짯tance value, in ohms, that deter짯mi짯nes how a com짯ple짯ted memo짯ry signal is ter짯mi짯na짯ted. Hig짯her values can help sta짯bi짯li짯ze hig짯her data rates. Values in the ran짯ge of 6096 can pro짯ve helpful. Inte짯ger values (ohms)
Memo짯ry clocks Added divi짯ders for memo짯ry clocks up to DDR4-4000 wit짯hout ref짯clk adjus짯t짯ment. Plea짯se note that values grea짯ter than DDR4-2667 is over짯clo짯cking. Your mileage may vary (as noted by our big over짯clo짯cking wart짯ning at the end of this blog). 133.33MT/s inter짯vals (2667, 2933, 3067, 3200, 3333, 3466, 3600, 3733, 3866, 4000)
Gear짯down Mode Allows the DRAM device to run off its intern짯al짯ly-gene짯ra짯ted 쩍 rate clock for lat짯ching on the com짯mand or address buses. ON is the default for speeds grea짯ter than DDR4-2667, howe짯ver the bene짯fit of ON vs. OFF will vary from memo짯ry kit to memo짯ry kit. Enab짯ling Gear짯down Mode will over짯ri짯de your cur짯rent com짯mand rate. On/Off
DRAM Power Down Can mode짯st짯ly save sys짯tem power, at the expen짯se of hig짯her DRAM laten짯cy, by put짯ting DRAM into a quie짯s짯cent sta짯te after a peri짯od of inactivity. On/Off
Com짯mand rate (CR) The amount of time, in cycles, bet짯ween when a DRAM chip is sel짯ec짯ted and a com짯mand is exe짯cu짯ted. 2T CR can be very bene짯fi짯ci짯al for sta짯bi짯li짯ty with high memo짯ry clocks, or for 4DIMM configurations. 2T, 1T
CLDO_VDDP Vol짯ta짯ge for the DDR4 PHY on the SoC. Some짯what coun짯ter짯in짯tui짯tively, lowe짯ring VDDP can often be more bene짯fi짯ci짯al for sta짯bi짯li짯ty than rai짯sing CLDO_VDDP. Advan짯ced over짯clo짯ckers should also know that alte짯ring CLDO_VDDP can move or resol짯ve memo짯ry holes. Small chan짯ges to VDDP can have a big effect, and VDDP should not be set to a value grea짯ter than VDIMM0.1V. A cold reboot is requi짯red if you alter this voltage.

 

Siden짯ote: pre1.0.0.6 BIO짯Ses may also have an ent짯ry labe짯led VDDP that alters the exter짯nal vol짯ta짯ge level sent to the CPU VDDP pins. This is not the same para짯me짯ter as CLDO_VDDP in AGESA 1.0.0.6.

Inte짯ger values