In seinem Blog hat AMD einen Ausblick auf das AGESA-Update 220.127.116.11 gewährt. AGESA steht für AMD Generic Encapsulated System Architecture und bildet das Grundgerüst zur Initialisierung von AMD-Prozessoren in der Phase des Power-On-Self-Test (POST) nach dem Einschalten des Systems. Darauf basierend entwickeln die Mainboard-Hersteller ihre Firmware (alias BIOS alias UEFI).
Wie bereits in einem früheren Blogbeitrag verraten, will AMD mit dem Update 18.104.22.168 die hohen DRAM-Overclocking-Frequenzen angehen. Mit Overclocking meint AMD alles über DDR4-2667, der höchsten offiziell für Ryzen freigegebenen Speichertaktrate. So sollen künftig auch Frequenzen über 3200 MHz einstellbar und vor allem stabil nutzbar sein, denn dass Ryzen eine zickige Diva in Sachen Speicherkompatibilität sein kann, haben wir ja schon mehrfach thematisiert.
Doch das AGESA-Update 22.214.171.124 soll noch weitere Features freischalten. So soll es mit IOMMU Groups möglich sein, Virtuellen Maschinen einzelne Grafikkarten zuzuweisen:
This capability is especially useful for users that want 3D-accelerated graphics inside a virtual machine. With ACS support, it is possible to split a 2‑GPU system such that a host Linux® OS and a Windows VM both have a dedicated graphics cards. The virtual machine can access all the capabilities of the dedicated GPU, and run games inside the virtual machine at near-native performance.
Abgesehen davon verspricht AMD 26 neue Features, darunter endlich die manuelle Konfigurierbarkeit der DRAM Command Rate.
|tWTR_S||Write to read delay (short), or the time between a write transaction and read command on a different bank group.||Integer values (cycles)|
|tWTR_L||Write to read delay (long), or the time between a write transaction and read command on the same bank group.||Integer values (cycles)|
|tWR||Write recovery time, or the time that must elapse between a valid write operation and the precharging of another bank. Higher values are often beneficial for stability, and values < 8 can quickly corrupt data stored in RAM.||Integer values (ns)|
|tWR||Write recovery time, or the time that must elapse between a valid write operation and the precharging of another bank. Higher values are often better for stability.||Integer values (ns)|
|tWCL/tWL/tCWL||CAS Write Latency, or the amount of time it takes to write to the open memory bank. WCL is generally configured equal to CAS or CAS‑1. This can be a significant timing for stability, and lower values often prove better.||Integer values (cycles)|
|tRTP||Read to precharge time, or the number of clock cycles between a READ command to a row and a precharge command to the same rank.||Integer values (cycles)|
|tRRD_S||Activate to activate delay (short), or the number of clock cycles between activate commands in a different bank group.||Integer values (cycles)|
|tRRD_L||Activate to activate delay (long), or the number of clock cycles between activate commands in the same bank group.||Integer values (cycles)|
|tRFC4||Refresh cycle time for quad frequency (4x) mode. This is typically a timing automatically derived from other values.||Integer values (cycles)|
|tRFC2||Refresh cycle time for double frequency (2x) mode. This is typically a timing automatically derived from other values.||Integer values (cycles)|
|tRFC||Refresh cycle time, or the time it takes for the memory to read and re-write information to the same DRAM cell for the purposes of preserving information. This is typically a timing automatically derived from other values.||Integer values (cycles)|
|tRDWR / tWRRD||Read-to-write and write-to-read latency, or the time that must elapse between issuing sequential read/write or write/read commands.||Integer values (cycles)|
|tRDRD / tWRWR||Read-to-read and write-to-write latency, or the time between sequential read or write requests (e.g. DIMM-to-DIMM, or across ranks). Lower values can significantly improve DRAM throughput, but high memory clocks often demand relaxed timings.||Integer values (cycles)|
|tRC||Row cycle time, or the number of clock cycles required for a memory row to complete a full operational cycle. Lower values can notably improve performance, but should not be set lower than tRP+tRAS for stability reasons.||Integer values (cycles)|
|tMAW||Maximum activation window, or the maximum number of times a DRAM row can be activated before adjacent memory rows must be refreshed to preserve data.||Integer values (cycles)|
|tMAC||Maximum activate count, or the number of times a row is activated by the system before adjacent row refresh. Must be equal to or less than tMAW.||Integer values (cycles)|
|tFAW||Four activation window, or the time that must elapse before new memory banks can be activated after four ACTIVATE commands have been issued. Configured to a minumum 4x tRRD_S, but values >8x tRRD_S are often used for stability.||Integer values (ns)|
|Rtt||Controls the performance of DRAM internal termination resistors during nominal, write, and park states.||Nom(inal), WR(ite), and Park integers (ohms)|
|ProcODT (CPU on-die termination)||A resistance value, in ohms, that determines how a completed memory signal is terminated. Higher values can help stabilize higher data rates. Values in the range of 60–96 can prove helpful.||Integer values (ohms)|
|Memory clocks||Added dividers for memory clocks up to DDR4-4000 without refclk adjustment. Please note that values greater than DDR4-2667 is overclocking. Your mileage may vary (as noted by our big overclocking wartning at the end of this blog).||133.33MT/s intervals (2667, 2933, 3067, 3200, 3333, 3466, 3600, 3733, 3866, 4000)|
|Geardown Mode||Allows the DRAM device to run off its internally-generated ½ rate clock for latching on the command or address buses. ON is the default for speeds greater than DDR4-2667, however the benefit of ON vs. OFF will vary from memory kit to memory kit. Enabling Geardown Mode will override your current command rate.||On/Off|
|DRAM Power Down||Can modestly save system power, at the expense of higher DRAM latency, by putting DRAM into a quiescent state after a period of inactivity.||On/Off|
|Command rate (CR)||The amount of time, in cycles, between when a DRAM chip is selected and a command is executed. 2T CR can be very beneficial for stability with high memory clocks, or for 4‑DIMM configurations.||2T, 1T|
|CLDO_VDDP||Voltage for the DDR4 PHY on the SoC. Somewhat counterintuitively, lowering VDDP can often be more beneficial for stability than raising CLDO_VDDP. Advanced overclockers should also know that altering CLDO_VDDP can move or resolve memory holes. Small changes to VDDP can have a big effect, and VDDP should not be set to a value greater than VDIMM‑0.1V. A cold reboot is required if you alter this voltage.
Sidenote: pre‑126.96.36.199 BIOSes may also have an entry labeled “VDDP” that alters the external voltage level sent to the CPU VDDP pins. This is not the same parameter as CLDO_VDDP in AGESA 188.8.131.52.